NXP Semiconductors QorIQ LS1028A, Reference Manual, Page: 50 / 112

Table 27. Reset sequence (continued)
Controller Step Action Description
7 Processor reset. The LS1028A processor begins loading RCW data from
the specified RCW source location.
When RCW loading is complete, the LS1028A processor
de-asserts HRESET_B and ASLEEP.
If RCW data is correct, then the system starts running the
code. If there is an error, then RESET_REQ_B is asserted
and the system halts.
8 Reset sequence complete. The CPLD has finished reset management.
The reset sequencer watches for reset switch events and
will restart at reset sequencer step 1 if any are detected.
LS1028ARDB Functional Description
QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018
50
COMPANY CONFIDENTIAL NXP Semiconductors