NXP Semiconductors QorIQ LS1028A, Reference Manual, Page: 12 / 112

Table 3. LS1028ARDB features (continued)
LS1028ARDB feature Specification Description
SerDes clocks REF_CLK1 and REF_CLK2 of 100 MHz
Ethernet clocks 125 MHz clock to Ethernet controller either from the IEEE 1588 port or an
onboard oscillator
Display Port clock
(DP_REFCLK) 27 MHz
FPGA CLK 25 MHz clock to CPLD
Power supplies
• 12 V input power from DC input adaptor
• 5.0 V for USB1, USB2, CAN1, CAN2, and mikro-click modules
• 1.0 V (VDD) for core and platforms
• Filtered 1.0 V / 0.9 V USB_SDVDD, USB_SVDD, DP_SVDD, SVDD
• 3.3 V for board components (SGMII PHY, M.2 connectors, SD card,
eMMC, CAN transceivers, mikroBUS connectors, LEDs, DP port,
CPLD IO and VDD, clockgen VDDO)
• Filtered 3.3 V for USB_HVDD
• 1.8 V for board components (UART transceivers, XSPI memories,
eMMC memory IO VDD, CPLD IO bank3)
• 1.8 V clockgen VDD and VDDA
• 1.8 V OVDD, TH_VDD
• Filtered 1.35 V X1VDD, AVDD_SD1_PLL1, AVDD_SD1_PLL2
• 2.5 V QSGMII PHY VDD25, VDD25A, and DDR4 memory VPP
• 1.0 V QSGMII PHY VDD, VDDA
• 1.2 V DRAM VDD
• 0.6 V DRAM VTT, VREF
• 3.3 V / 1.8 V EVDD for eSDHC
• 0.9 V / 1.0 V TA_BB_VDD
Debug interface
• Arm Cortex 10-pin JTAG connector
• CPLD programming header
Package
• Package type is Flip Chip, Plastic-ball, Grid Array (FC-PBGA), 17 mm
x 17 mm
• Socket and heat sink are included
Table continues on the next page...
LS1028ARDB Overview
QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018
12
COMPANY CONFIDENTIAL NXP Semiconductors