NXP Semiconductors QorIQ LS1028A, Reference Manual, Page: 24 / 112

1V2
}
VTT
0.6V
D1_MDQS[3:0]
D1_MDQ[31:0]
D1_MDM[3:0],8
D1_MRAS / MCAS / MWE / MACT
D1_MA[13:0]
D1_MBA[1:0]
3V3
MC34716E P
D1_MAPAR / MBG[1:0]
D1_MDIC1
D1_MDIC0
G1VDD
D1_TPA
I2C1_CH0
G1VDD
TP
Addr.= 0x51
D1_MCK[1:0] / MODT[1:0]
D1_MCS [1:0]
LS1028A
RS T_LV_ME M_B
RS T_ME M_B
from CP LD
VREF CA
0V6
DDR4 S DRAM
MT40A1G8S A-075:E
1G x8 discreet chip(5nos)
4 Data byte lanes + E CC
S PD
E E PROM
D1_MCKE [1:0]
DQ[7:0]
DQ[15:8]
DQ[23:16]
DQ[31:24]
E CC[3:0]
D1_MECC[3:0]
T
E
R
M
I
N
A
T
I
O
N
VDD
1V2
VPP
2V5
GVDD
1V2
MVRE F
GND
Fly-by
Topology
1V2 3V3
0V6 VTT
0V6 VRE F
D1_MALE RT
1.0K
1V2
3V3
VDD/GVDD
PS
VTT source/sink
Vrefca
74AUP1G07GW
Figure 8. DDR4 interface
2.5 USB interface
The LS1028ARDB supports two USB 3.0 ports. The USB 1 port is connected to a Type A connector and is configured as host.
Type A connector is always host only. The USB2 port is connected to a Type C connector and is configured as downstream facing
port (DFP) or upstream facing port (UFP). Based on the configuration detected on the Type C port, the USB2 PHY can operate
either in host or device mode. The following figure shows the architecture of the USB 3.0 interface.
LS1028ARDB Functional Description
QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018
24
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