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200ohm

10

LS1028A

5V0

USB

3.0

type C

USB 2_DRVVB US

USB 2_RESRE F

USB 2_PWRFAULT

USB 2_VB US

“USB2”

90

W 

diff. imp.

USB 2_D_[P,M]

USB 2_ID

USB 2_TX_[P,M]
USB 2_RX_[P,M]

<=2A

USB2

NX5P3090

5V0

USB 1_DRVVB US

USB 1_RESRE F

USB 1_PWRFAULT

USB 1_VB US

“USB1”

90

W 

diff. imp.

USB 1_DP,DM

USB 1_ID

USB 1_TXP,TXM

USB 1_RXP,RXM

<=2A

USB1

NX5P3090

USB

3.0

Type-A

200ohm

HS

Mux

CB TU02043

USB1_SEL

PTN5150A

CC1

CC2

EXT_SE L

TX1_[P,M]

TX2_[P,M]

RX1_[P,M]

RX2_[P,M]

CPLD

CON_DET

VB US_EN

USB2_ID

USB2_DRVVBUS

Figure 9. USB architecture

The PTN5150A (from NXP) is a small low-power configuration channel logic chip that detects (through CC1 and CC2 pins) and
indicates to the USB controller (through USB2_ID signal) if the USB2 Type C connector is configured as a device or host. The
PTN5150A is configured to operate the USB3 Type C port in DFP mode with default USB current capability (0.5 A / 0.9 A). To
support higher current on the Type C (USB2) port, the hardware configuration of PTN5150 and NX5P3090UK VBUS switch should
be changed. Refer to the device datasheet for more information.

The USBx_DRVVBUS and USBx_PWRFAULT pins of each USB controller are connected to a programmable-current USB switch,
NX5P3090UK (from NXP), for individual port management. The USB switch is powered from +5 V USB power supply. To indicate
power fault conditions, the USB switch sends PWRFAULT signals to the USB controller. For USB2 port, the USB switch drives
USB2 VBUS (USB2_VBUS) when USB2_DRVVBUS=1, USB1_ID = 0, and USB2_CON_DET=1, this logic is controlled by CPLD.
For USB1 port, the USB switch drives USB1 VBUS (USB1_VBUS) when USB1_DRVVBUS=1.

The maximum allowed current consumption of a USB connected device is 900 mA per channel.

Both, USB1 and USB2 connectors have an LED nearby, USB1_5V and USB2_5V, respectively, which are active when the +5 V
USB power supply is enabled to the connectors.

USB interface

QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018

NXP Semiconductors

COMPANY CONFIDENTIAL

25

Summary of Contents for QorIQ LS1028A

Page 1: ...QorIQ LS1028A Reference Design Board Reference Manual NXP Semiconductors Document Number LS1028ARDBRM Reference Manual Rev b 11 2018 COMPANY CONFIDENTIAL...

Page 2: ...0 2 17 Mikro click modules 41 2 18 GPIOs 43 2 19 Interrupt handling 43 2 20 Temperature measurement 44 2 21 System controller 44 Chapter 3 Board Configuration and Debug Support 51 3 1 Switch configura...

Page 3: ...n Registers 90 4 40 Board Configuration 0 BRDCFG0 91 4 41 Board Configuration 1 BRDCFG1 92 4 42 Board Configuration 2 BRDCFG2 92 4 43 Board Configuration 3 BRDCFG3 93 4 44 Board Configuration 4 BRDCFG...

Page 4: ...applies to the board with the LS1043A interposer unless otherwise noted NOTE Developers using the LS1028ARDB can perform standard debugging tasks such as Upload and run code Set breakpoints Display me...

Page 5: ...High level data link control HSSI High speed serial interface I2C Inter integrated circuit JTAG Joint Test Action Group IEEE Standard 1149 1 LOS Loss of signal OCM Offline configuration manager OTG O...

Page 6: ...under a non disclosure agreement NDA To request access to these documents contact your local field applications engineer or sales representative Table 2 Related documentation Document Description Link...

Page 7: ...and explore the features of the LS1028A SoC Contact FAE sales representative CodeWarrior Development Studio for QorIQ LS series ARM V8 ISA Targeting Manual This manual explains how to use the CodeWarr...

Page 8: ...1 LS1028A block diagram The figure below shows the LS1028ARDB block diagram LS1028ARDB Overview QorIQ LS1028A Reference Design Board Reference Manual Rev b 11 2018 8 COMPANY CONFIDENTIAL NXP Semicond...

Page 9: ...LK x2 CAN2 Standard Display CAN1 Standard Display CAN Transciever TJ A1051 CAN Transciever TJ A1051 x4 RJ 45 with Transform er RJ 45 with Transform er Rmux A B C D eMMC 8GB MTFC8GAKAJ CN 1M WT Mux Mux...

Page 10: ...rts one 1 GbE RJ45 SGMII connected through the Qualcomm AR8033 PHY Lane 1 Supports four 1 25 GbE RJ45 QSGMII each connected through the NXP F104S8A PHY Lane 2 Connects to one PCIe M 2 Key E slot to su...

Page 11: ...four 1 GB Ethernet ports IEEE 1588 Five 1G 100M 10BaseT Ethernet ports supported One port is supported on SGMII ENET MAC and the other four through the TSN switch Five RJ45 connectors with link and a...

Page 12: ...oBUS connectors LEDs DP port CPLD IO and VDD clockgen VDDO Filtered 3 3 V for USB_HVDD 1 8 V for board components UART transceivers XSPI memories eMMC memory IO VDD CPLD IO bank3 1 8 V clockgen VDD an...

Page 13: ...LD Manages the following System reset sequencing SoC POR configuration at reset Implements registers for system control and monitoring General fault monitoring and logging Board features QorIQ LS1028A...

Page 14: ...click modules on page 41 GPIOs on page 43 Interrupt handling on page 43 Temperature measurement on page 44 System controller on page 44 2 1 Processor The LS1028ARDB board is based on the QorIQ LS1028A...

Page 15: ...P_SVDD 12V0 J 5 12V 5A Adaptor CHASSIS FAN1 LTC7151S VIN PS_VDD_PG LED LTC7151S VIN PS_3V3_PG LED 3 3V 3 3V 15A VDD 3V3 PS_3V3_PG LT8609S E V VIN PS_5V0_PG 5 0V 5V 2A 5V0 LPF x2 LS1028 USB_HVDD USB_HV...

Page 16: ...Q VTT VREF VDDQ SINK SOURCE DDR TE RMINATION REGULATOR PS_DDR_EN PS_DDRREG_PG_B VTT 0 60V 3A VREFCA_S 0 60V 3A To CPLD 3V3 DRAM VTT DRAM VREFCA_S LS1028 VCC_GVDD VCC_GVDD_S DRAM VDD SD_B 3V3 PVIN1 4 V...

Page 17: ...he LS1028A core supplies Filtered VDD also powers USB USB_SDVDD USB_SVDD Display Port DP_SVDD and SerDes SVDD power supplies of LS1028A NOTE U3 LTC7151S Linear Technology 3V3 3 3 V at 15 A Supplies po...

Page 18: ...utputs are SW1LX 1 0 V for the QSGMII PHY VDD and VDDA SW2LX 2 5 V for QSGMII PHY VDD25 VDD25A and DDR4 memory VPP SW3LX 1 35 V Filtered 1 35 V is supplied to LS1028A X1VDD AVDD_SD1_PLL1 and AVDD_SD1_...

Page 19: ...pon the state of GPIO1_DAT24 GPIO pin of LS1028A 2 2 3 Power supply sequence The LS1028ARDB board is configured to switch ON automatically when the 12 V power supply is switched ON and is connected to...

Page 20: ...Q5 internally programmed 1 0V LDO2 LTC7151S VDD VDD 0 9 1V VR500 SW1 LDO2 soft start after LDO2 PS_VDD_EN tss MC34716 DDR4 1 2V VTT VREF VR500 SEQ8 internally programmed VR500 LDO4 LDO4 soft start aft...

Page 21: ...N E C1_R X_CLK DP_REF CLK_P N DIFF _S YS CLK_ P N 27 MHz LVDS PE x Conn 100 MHz LP HCS L 3 S LOTn_REFCL K_ P N S D1_RE F_CLK 1 2 Differential S ingle ended 1588 Header 125 00 MHz 1 8V LVCMOS 3 S LOT 1...

Page 22: ...N SD1_REF_CLK2_ P N Frequency 100 MHz Output type LP HCSL Operating voltage 1 8 V SerDes1 controller OUT6 71 PEXM2_1_REFCLK_ P N PEXM2_2_REFCLK_ P N Frequency 100 MHz Output type LP HCSL Operating vol...

Page 23: ...memory chips supporting data transfer rates of up to 1 6 GT s and one 1G x8 DDR4 SDRAM memory chip for supporting ECC The address and control command signals to the DDR4 SDRAM memory chips are routed...

Page 24: ...RE F D1_MALERT 1 0K 1V2 3V3 VDD GVDD PS VTT source sink Vrefca 74AUP1G07GW Figure 8 DDR4 interface 2 5 USB interface The LS1028ARDB supports two USB 3 0 ports The USB 1 port is connected to a Type A c...

Page 25: ...igher current on the Type C USB2 port the hardware configuration of PTN5150 and NX5P3090UK VBUS switch should be changed Refer to the device datasheet for more information The USBx_DRVVBUS and USBx_PW...

Page 26: ...through the CPLD register 2 7 SerDes interface The LS1028A processor supports one SerDes LYNX36 module with four high speed serial communication lanes to support various protocols such as SGMII QSGMII...

Page 27: ...ansceiver through TX signals only and an SGMII port over LYNX36 SerDes Lane A The controller also supports QSGMII connectivity through the TSN switch and it is available over LYNX36 SerDes interface L...

Page 28: ...ECx_GTX_CLK 1588_PULSE _OUT 2 1588 1PPS SERDES RX LANE A TX 2V5 TRANS LATOR MAX14591 1 8V 2 5V TRANS LATOR MAX14591 1 8V 2 5V TRANS LATOR MAX14591 1 8V 2 5V E 1_RXD0 PHYADDR 0 E 1_RXD1 PHYADDR 1 E 1_A...

Page 29: ...N P3_D1P N P3_D3P N P3_D2P N OUT1 LVDS 100MHz Figure 12 QSGMII port Table 9 Hardware bootstrap settings for QSGMII PHY Setting Description PHY_AD 4 2 PHY address 0b100 MODE REFCLK_SEL 1 0 00 125 MHz i...

Page 30: ...lability with Audio 1588_PULSE_OUT2 1PPS IEEE1588 J12 SMA connector Yes 1588_CLK_OUT IEEE1588 J11 IEEE1588 header Yes 1588_ALARM_OUT 1 IEEE1588 J11 IEEE1588 header No 1588_PULSE_OUT11 IEEE1588 J11 IEE...

Page 31: ...EE header 1 IEEE signals connect to the SAI4 CODEC 2 10 M 2 connectors The LS1028ARDB supports M 2 connectors Key E and Key B that are supported through SerDes lanes 2 and 3 One M 2 Key E connector J1...

Page 32: ...or PCIe Gen 1 and Gen 2 compliant endpoints For more detail on these adapters click the following links P11S P11F M 2 NGFF to PCI E Extender Board P11S P11F Duo PCI E to M 2 NGFF Extender Board 2 11 D...

Page 33: ...UX_UART2_SEL0 BRDCFG3 5 4 SW2 5 6 0x UART2 on DB9 connector default value 10 UART2 on mikro click module 1 11 UART2 on mikro click module 2 2 12 CAN interface The LS1028A processor supports two contro...

Page 34: ...nd WP CAN 1 and 2 interfaces GPIO and USB2 PWRFAULT DRVVBUS These secondary functionalities should be enabled in the RCW field The I2C1 port is connected to a PCA9847PWJ I2C multiplexer to isolate add...

Page 35: ...r the I2C1 bus partitions the bus into eight sub buses called channels Software must program the multiplexer to access one of the eight I2C1 channels All boot software dependant devices are placed on...

Page 36: ...VBAT 3V3 3V3 3V3 I2C1_CH6 MikroClick Module 1 MikroClick Module 1 MikroClick Module 2 MikroClick Module 2 1V8 NXP S GTL5000 From PCA9847 Figure 17 I2C1 channels The following table describes the devi...

Page 37: ...r monitor Reports voltage current and power data for VDD I2C1_CH3 0x4C NXP SA56004ED Thermal monitor Monitors processor thermal diode 0x51 NXP PCF2129AT Battery backed clock Provides time and date fun...

Page 38: ...he QSPI emulator through two high speed multiplexers The XSPI memories and QSPI emulator supports single mode data transfer at boot additionally NOR flash memory supports octal mode NAND flash memory...

Page 39: ...apter The EM100Pro emulator uses 1 8 V as the input output voltage The table below describes the XSPI routing configuration Table 17 XSPI configuration Configuration signal DIP switch CPLD register De...

Page 40: ...10K 10K 4x 1V8 1V8 1V8 1V8 8 6 9 7 5 3 4 2 1 10 to CPLD 1 8V OVDD 1 8V Figure 19 JTAG architecture 2 16 eSDHC interface The LS1028A processor supports two enhanced secured digital host controllers eSD...

Page 41: ...V To move from UHS state to default or high speed state of SD card a power reset is required NOTE I2C2 must be programmed in the RCW to serve as the card detect CD_B and write protect WP pins for the...

Page 42: ...number Description BLE module BLE P Click SPI MIKROE 1597 Module supports Bluetooth 4 0 on the board This module communicates with LS1028ARDB through SPI CS SCK MISO MOSI INT RDY and AN ACT lines on m...

Page 43: ...channel 6 or channel 7 respectively 2 18 GPIOs The GPIOs used on the LS1028ARDB are GPIO1_DAT 24 GPIO1_DAT 25 and GPIO3_DAT 2 4 Apart from these GPIOs all signals UART SPI PWM coming on connectors mik...

Page 44: ...ribed in the following table Table 24 Thermal monitor configuration I2C write Description 0x77 0x0B 0x0B Program primary I2C bus multiplexer PCA9848PWJ to get access to I2C1_CH3 I2C sub channel for SA...

Page 45: ...resistors to encode P CB rev RST_I2C_B to I2C devices HOT_CLK HOT_RST_B 10K 10uF 1V8 from CLOCK RST_MEM1_3V3_B 25 MHz 1 8V LVCMOS 3x BOM_REV 2 0 000 Base Rev 0 001 Rev 1 Selectively DNP resistors toen...

Page 46: ...L_B SW_SVR 0 1 SW_UART2MAP 1 0 SW_UCLICK_PWMMAP SW_UCLICK_SP IMAP SW_CPU_FORCE 1 0 SW_BYPASS_B SW_CFG_WP SW_BOOTBOX_B CPLD_PROG_TDI CPLD_PROG_TDO CPLD_PROG_TCK CPLD_PROG_TMS 8 6 9 7 5 3 4 2 1 10 3 3V...

Page 47: ...SRC0 UART2_SOUT SW1 1 4 DUTCFG0 3 0 Specifies RCW fetch location CFG_RCW_SRC1 UART1_SOUT CFG_RCW_SRC2 ASLEEP CFG_RCW_SRC3 CLK_OUT TEST_SEL_B1 TEST_SEL SW3 1 DUTCFG2 0 Silicon variations CFG_SVR 0 1 XS...

Page 48: ...ing The system controller manages the reset sequencing during the system startup After successful power sequencing all power good are reported from power supplies reset sequencer asserts the PORESET_B...

Page 49: ...uration signals are driven CFG_XSPI_MAP 0 3 CFG_MUX_I2C2 CFG_MUX_I2C3 CFG_MEM_WP CFG_MUX_UART2_SEL0 CFG_MUX_uBUS1_UART_B CFG_MUX_uBUS2_UART_B CFG_MUX_uBUS1_SPI_B CFG_MUX_uBUS2_SPI_B CFG_MUX_uBUS1_PWM_...

Page 50: ...RCW data is correct then the system starts running the code If there is an error then RESET_REQ_B is asserted and the system halts 8 Reset sequence complete The CPLD has finished reset management The...

Page 51: ...tch is up on the value is 1 If the switch is down off the value is 0 Table 28 Switch settings Switch Supported function Description SW2 1 4 RCW fetch location CFG_RCW_SRC 3 0 SW_RCW_SRC 3 0 0000 Hard...

Page 52: ..._B SW_SVR 0 1 011 LS1018AN E 111 LS1028AN E default value SW3 5 6 UART2 configuration CFG_MUX_UART2_SEL0 SW_UART2MAP 1 0 0x UART2 on DB9 connector default value 10 UART2 on mikro click module 1 11 UAR...

Page 53: ...Unused Reserved Default value is 0 SW5 8 IEEE SAI 0 Signals routed to IEEE1588 connector 1 Signals routed to TX only SAI transceiver The table below summarizes the default switch settings of the LS102...

Page 54: ...dicates Improper RCW source selection Boot memory does not contain a valid RCW PBL PLL multipliers in the RCW data are not compatible with the fixed SYSCLK DDRCLK or SDCLK values D26 Red FAIL Indicate...

Page 55: ...nel of the LS1028ARDB board chassis Table 32 LEDs available on front panel of board chassis Reference designator LED color LED name Description when LED is ON D27 Red RESET RESET is ON when reset to D...

Page 56: ...t applicable M1 Not applicable M0 Heartbeat Clock monitor Table 34 Reset sequencer state State LED M 3 0 Description IDLE 0000 0x0 Waiting for initial reset events SAMPLE 0001 0x1 Sample configuration...

Page 57: ...cause Register bit set RST_BY_SW 1101 0xD Start reset due to cause Pushbutton switch RECONFIG 1110 0xE Start reset due to cause Reconfig request POST_RST 1111 0xF Recover from requester reset LEDs Qor...

Page 58: ...ID 8 RO 01000111b 001h Board Version VER 8 RO 00010001b 002h Qixis Version QVER 8 RO 00000001b 003h Programming Model MODEL 8 RO 01000000b 004h Minor Revision MINOR 8 RW 00000101b 005h General Contro...

Page 59: ...2 RST_MASK3 8 RW 00000000b 050h Board Configuration 0 BRDCFG0 8 RW xxx00000b 051h Board Configuration 1 BRDCFG1 8 RO 0000xxxxb 052h Board Configuration 2 BRDCFG2 8 RO 00000000b 053h Board Configuratio...

Page 60: ...t define all bits reserved bits behave as follows Reserved Bits Register Recommended Actions DUTCFG Read as 1 Write ones to unused bits others Read as 0 Write zeroes to unused bits Future definitions...

Page 61: ...gisters contain values which identify the board including major revisions to the board and or system controller FPGA or CPLD 4 4 Identification ID Address Register Offset ID 000h Function The ID regis...

Page 62: ...2 etc 3 0 BRD PCB board version 1 Rev A or pre release 2 Rev B etc The ARCH field is used by QIXIS and software to handle architecture changes The ARCH field allows the use of a common QIXIS image acr...

Page 63: ...0 R QVER W NONE 00000001 Fields Field Function 7 0 QVER Qixis version as a decimal value 1 Version 1 2 Version 2 4 7 Programming Model MODEL Address Register Offset MODEL 003h Function The MODEL regi...

Page 64: ...PCB version is A2 B2 etc and so forth Note that this field should be appended to the VER PCB information only if non zero 4 8 Minor Revision MINOR Address Register Offset MINOR 004h Function The MINOR...

Page 65: ...erved fields are found only in QDS QTAG but are present for compatibility Contents are as follows MINTAG Definition Address Range Name Definition 0x00 0x03 TAG not implemented 0x05 0x06 MINOR Minor bu...

Page 66: ...7 6 5 4 3 2 1 0 R SWLED XTEST LED FAIL W CRST 00 0 0 00 0 0 Fields Field Function 7 6 SWLED Controls front panel power switch LEDs when CTL LED is set 5 Reserved 4 XTEST This bit directly drives the...

Page 67: ...ster Offset AUX 006h Function The AUX register may be used by software to store information The AUX register is initialized to zero when the system is powered up and never altered by hardware again Di...

Page 68: ...SLEEP Reporting 0 At least one core is actively operating 1 All cores are in sleep mode 0 Reserved 4 13 Alarm ALARM Address Register Offset ALARM 00Ah Function The ALARM register detects and reports a...

Page 69: ...upon software programming 0 TALERT Temperature Alert 0 The temperature is within normal limits 1 The temperature has exceeded fault limits NOTE This signal may be asserted by either SA56004 thermal m...

Page 70: ...talled 4 FORCED Processor Override 0 Processor type CPUID is based on device 1 Processor type CPUID was overridden using SW_CPU_FORCE 3 0 Reserved 4 15 Presence Detect 2 STAT_PRES2 Address Register Of...

Page 71: ...nector 2 PEX 1 no module is detected 0 M2_1 0 a module is detected in M 2 connector 1 PEX 1 no module is detected 4 16 LED Control LED Address Register Offset LED 00Eh Function The LED register can be...

Page 72: ...alter the configuration of the board or processor into different voltages SYSCLK frequencies boot device selections or any other configuration controlled by a BRDCFG or DUTCFG register 4 18 Reconfigu...

Page 73: ...disabled within 2 29 clock cycles 8 minutes the system is reset NOTE This is not a highly secure watchdog software can reset this bit at any time and disable the watchdog 2 1 Reserved 0 GO Reconfigura...

Page 74: ...d 0 U2ID USB2 ID Status 0 USB2 ID is low DFP mode 1 USB2 ID is high UFP mode 4 20 USB Control USB_CTL Address Register Offset USB_CTL 01Eh Function The USB_CTL register manages USB features principall...

Page 75: ...CH register selects the watchdog timer value used during the reconfiguration processes When RCFG WDEN enables the watchdog timer a count down timer begins If the DUT software does not disable or resta...

Page 76: ...bility to monitor general power status as well as individual power status for those supplies that have reporting capability Other registers provide limited power control features most power control is...

Page 77: ...wered up 6 0 Reserved 4 24 Power Status 0 PWR_MSTAT Address Register Offset PWR_MSTAT 024h Function The PWR_MSTAT register monitors the overall power status of the board including that of the main ATX...

Page 78: ...shutdown for some reason Check the ALARM register for details 3 PWROK General Power Status 0 One or more power supplies are off or not yet stable 1 All power supplies are on and stable 2 Reserved 1 0...

Page 79: ...ult 0 DP_PWR is faulted overcurrent 1 DP_PWR is operating 3 DDR DDR Power Supplies GVDD VTT MVREF Status 0 Power supplies are disabled or faulted 1 Power supply are operating 2 P5V 5V0 Power Supply St...

Page 80: ...om switches for the SYSCLK and DDRCLK clocks Values in the CLK_SPD1 register are used by boot software accurately initialize timing dependent parameters such as for UART baud rates I2C clock rates and...

Page 81: ...ts 7 6 5 4 3 2 1 0 R ID W NONE 0000 0000 Fields Field Function 7 4 Reserved 3 0 ID System Clock ID 0000 NONE CLK0 SYSCLK is fixed on this system 4 29 Reset Control Registers The reset control register...

Page 82: ...asserted to the DDR DIMMs devices With proper DDR controller setup and careful software setup DDR contents can survive resets This bit is not cleared with a general reset but is preserved as long as p...

Page 83: ...ate waiting for permission to proceed 6 SYSRST System Reset 0 System is operating normally 1 System is in reset 5 3 Reserved 2 HRST HRESET_B status 0 HRESET_B is not asserted 1 HRESET_B is asserted 1...

Page 84: ...reason See REASON field codes 3 0 REASON Reset Reason 0000 Power on reset 0001 COP JTAG HRESET_B was asserted 0010 reserved 0011 RST_CTL RST was set 0100 Reset switch chassis or on board was pushed 0...

Page 85: ...ing a resource while in used by the bootloader or OS will typically cause crashes etc Use carefully Diagram Bits 7 6 5 4 3 2 1 0 R XSPI I2CMUX EMMC MEM W CRST 0 00 0 0 00 0 Fields Field Function 7 XSP...

Page 86: ...H 1 Assert RST_ETH_B for the Qualcomm AR8033 PHY 5 3 Reserved 2 TRST 1 Assert DUT_TRST_B 1 HRST 1 Assert DUT_HRESET_B NOTE This bit only asserts the signal to the DUT it is not intended to be used as...

Page 87: ...7 6 5 4 3 2 1 0 R M2_1 M2_2 M2_3 IEEE W CRST 0 0 0 0000 0 Fields Field Function 7 M2_1 1 Assert RST_PEXM2_1_B 6 M2_2 1 Assert RST_PEXM2_2_B 5 M2_3 1 Assert RST_SATAM2_3_B 4 1 Reserved 0 IEEE 1 Force R...

Page 88: ...En refer to Table 5 53 for details Note that RST_MASK bits are cleared on AUX reset and so are usually only cleared by software This is very different from the RST_FORCE registers Diagram Bits 7 6 5 4...

Page 89: ...II ETH TRST HRST PORST W ARST 0 0 000 0 0 0 Fields Field Function 7 QSGMII 1 Mask RST_QSGMII_B 6 ETH 1 Mask RST_ETH_B for the RealTek PHY 5 3 Reserved 2 TRST 1 Mask DUT_TRST_B 1 HRST 1 Mask DUT_HRESET...

Page 90: ...Mask RST_SATAM2_3_B 4 1 Reserved 0 IEEE 1 Mask RST_IEEE1588_B 4 39 Board Configuration Registers This block of registers control the configuration of the board BRDCFG registers are always static drive...

Page 91: ...0 R XMAP W RRST SW_XMAP 00000 Fields Field Function 7 5 XMAP XMAP controls how XSPI_A chip selects are connected to devices peripherals XSPI_A_CS0 XSPI_A_CS1 000 sNOR sNAND 001 sNAND sNOR 010 EMU sNOR...

Page 92: ...nction 7 6 Reserved 5 4 Reserved 3 0 SYSCLK SYSCLK Frequency Selection 0010 100 00 MHz fixed All other values are reserved 4 42 Board Configuration 2 BRDCFG2 Address Register Offset BRDCFG2 052h Funct...

Page 93: ...ed 5 4 SD1CK2 SerDes1 Clock 2 Rate 00 100 000 MHz fixed 3 0 Reserved 4 43 Board Configuration 3 BRDCFG3 Address Register Offset BRDCFG3 053h Function The BRDCFG3 register controls board routing Board...

Page 94: ...RT2 nets CFG_MUX_UART2 00 Routed to RS232 transceiver and DB9 connector P1A default 01 reserved 10 Routed to uBUS1 module 11 Routed to uBUS2 module 3 GTA Controls whether GPIO3 can drive TA_TMP_DETECT...

Page 95: ...xpress M 2 Wireless disable net CFG_PEX2_WDIS_B 0 Board operates normally 1 Board wireless shutdown requested 5 SATASLP SATA DevSlp control net SATAM2_3_DEVSLP 0 SATA module operates normally 1 SATA m...

Page 96: ...1R U1IRQ U1RST W RRST X X X 0 00 00 Fields Field Function 7 U1A U1A reports the current 3 3V LVTTL level on the AN analog output pin 6 U1I U1I reports the current 3 3V LVTTL level on the IRQ interrupt...

Page 97: ...pin treated as output asserted low 11 RST pin treated as output asserted high 4 46 Board Configuration 6 BRDCFG6 Address Register Offset BRDCFG6 056h Function The BRDCFG6 register manages uBUS2 connec...

Page 98: ...put asserted low 11 RST pin treated as output asserted high 4 47 DUT Configuration Registers This block of registers control the configuration of the DUT Device Under Test DUTCFG registers unlike BRDC...

Page 99: ...4kB pages 1111 XSPI serial NOR 24bit address Note that the RCW_SRC settings are mapped to equivalent 9 bit values when an LS1043A interposer is connected 4 49 DUT Configuration 1 DUTCFG1 Address Regis...

Page 100: ...on 2 DUTCFG2 Address Register Offset DUTCFG2 062h Function The DUTCFG2 register manages device selection SVR and internal only device test features Diagram Bits 7 6 5 4 3 2 1 0 R SVR01 TEST W RRST 111...

Page 101: ...ion of these bits are defined by silicon engineers for special use Diagram Bits 7 6 5 4 3 2 1 0 R ENGUSE0 W RRST SW_ENGU 1111111 Fields Field Function 7 ENGUSE0 Controls cfg_enguse0 0 Processor uses d...

Page 102: ...n input mode are ignored Undefined pins read as 0 Diagram Bits 7 6 5 4 3 2 1 0 R IO4 IO3 IO2 W CRST 111 1 1 1 11 Fields Field Function 7 5 Reserved 4 IO4 IO port values if corresponding DIR n is 0 0 i...

Page 103: ...in is in input mode and can be accessed through the same GPIO1_IOn pin If a GPIO_DIR register bit is 1 the corresponding GPIO port pin is in output mode and GPIO1 port pins are set to the correspondin...

Page 104: ...nt live states of various IRQ EVT pins IRQ EVT signals have programmable polarities so no interpretation is made as to whether the signal is asserted or deasserted 4 56 Interrupt Status 0 IRQSTAT0 Add...

Page 105: ...t input IRQ_RTC_B 0 Interrupt is asserted 2 Reserved 1 UBUS2 Interrupt input IRQ_UBUS2_B 0 Interrupt is asserted 0 UBUS1 Interrupt input IRQ_UBUS1_B 0 Interrupt is asserted 4 57 Interrupt Status 1 IRQ...

Page 106: ...8 Interrupt Status 2 IRQSTAT2 Address Register Offset IRQSTAT2 092h Function Additional IRQ_STAT reporting see IRQSTAT0 for details Diagram Bits 7 6 5 4 3 2 1 0 R W NONE 11111111 Fields Field Function...

Page 107: ...ow 11 Drive TMP_DETECT_B high The status of TMP_DETECT_B can be monitored with the IRQSTAT registers 5 0 Reserved 4 60 Core Management Space Registers The core management address data registers allow...

Page 108: ..._A 00h nr Qixis_Get_Reg CMS_D for i 1 i nr i Qixis_Set_Reg CMS_A i printf SW 1d 02X n i Qixis_Get_Reg CMS_D 4 61 Core Management Address CMSA Address Register Offset CMSA 0D8h Function The CMSA regist...

Page 109: ...r Offset CMSD 0D9h Function CMSD contains the value of a CMS register selected by CMSA See CMSA for details Diagram Bits 7 6 5 4 3 2 1 0 R DATA W ARST 00000000 Fields Field Function 7 0 DATA Read writ...

Page 110: ...39 Clocks on page 21 Updated Table 6 LS1028ARDB clocks on page 22 Updated Figure 7 on page 21 Ethernet controller interface on page 27 Updated IEEE 1588 interface on page 29 section Updated Figure 11...

Page 111: ......

Page 112: ...nder its patent rights nor the rights of others NXP sells products pursuant to standard terms and conditions of sale which can be found at the following address nxp com SalesTermsandConditions While N...

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