NXP Semiconductors QorIQ LS1028A, Reference Manual, Page: 10 / 112

Table 3. LS1028ARDB features
LS1028ARDB feature Specification Description
Processor Two-core processor
Two Arm
®
Cortex
®
- A72 processor cores:
• Based on 64-bit ARMv8 architecture
• Up to 1.3 GHz operation
• Single-threaded cores with 48 KB L1 instruction cache and 32 KB L1
data cache
• Arranged as a single cluster of two cores sharing a single 1 MB L2
cache
For more details on the LS1028A processor, see QorIQ
LS1028A Family Reference Manual .
NOTE
DDR memory DDR4
• Five onboard 1G x8 discrete memory modules (Four data byte lanes
+ ECC)
• 32-bit data and 4-bit ECC
• One chip select
• Data transfer rates of up to 1.6 GT/s
• Single-bit error correction and double-bit error detection ECC (4-bit
check word across 32-bit data)
High-speed serial ports
(SerDes) One four-lane SerDes
• Lane 0: Supports one 1 GbE RJ45 SGMII, connected through the
Qualcomm AR8033 PHY
• Lane 1: Supports four 1.25 GbE RJ45 QSGMII, each connected
through the NXP F104S8A PHY
• Lane 2: Connects to one PCIe M.2 Key-E slot to support PCIe Gen3
(8 Gbit/s) cards
• Lane 3: Connects to one PCIe M.2 Key-E slot or one SATA M.2 Key-B
slot through a register mux to support either PCIe Gen 3 (8 Gbit/s) or
SATA Gen 3 cards (6 Gbit/s) at a time
eSDHC eSDHC1 Supports a secure digital (SD) connector for connecting an external SD
3.0 card
eSDHC2
• Onboard 8 GB eMMC memory (MTFC8GAKAJCN) supporting
— x1, x4, and x8 I/Os
— SDR/DDR modes up to 52 MHz clock speed
— HS200/HS400 modes
SPI SPI3 Connects to two mikroBUS
™
sockets to support mikro-click modules,
such as Bluetooth 4.0, 2.4 GHz IEEE 802.15.4 radio transceiver, near
field communications (NFC) controller
Table continues on the next page...
LS1028ARDB Overview
QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018
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