Appendix B
Revision history
This sections summarizes revisions to this document.
Table B-1. Revision history
Revision
Date
Section
Description
0
06/2016
Initial public release.
1
08/2016
Incorporated branding changes
2
08/2016
FRDM-LS1012A features
Double data rate (DDR) memory
QSPI interface
Updated DDR and QSPI memory sizes to bytes instead
of bits
3
12/2016
Reset and configuration signals
Updated
Table 2-5
table to remove components: R35
and R49
FRDM-LS1012A top view
Updated top view for Rev c board
FRDM-LS1012A block diagram
Updated FRDM-LS1012A block diagram for the Rev C
board
Voltage regulation
Updated
Table 2-3
to add "VCC_POVDD"
Clocks
In
Table 2-6
, updated:
• "25MHz (XTAL)" to "EXTAL (Bypass mode)"
• "Clock buffer, 524S" to "Oscillator
(KC2520C25.0000C1LE00) and Clock buffer,
524S"
I
2
C ports
Added device "MC34VR5100A1EP"
Revision control
Added details for GPIOs used to determine board
revision
FRDM-LS1012A board drawings
Updated top-side and bottom-side assembly drawings
GPIO pins
Updated
Table 2-11
to:
• Remove "SDHC1_VSEL" row
• Remove translators details from SDHC1 rows
QorIQ FRDM-LS1012A Board Reference Manual, Rev. 3, 12/2016
NXP Semiconductors
29