DUT_TCK
DUT_TMS
DUT_TDI
PORESET_B
DUT_TRST
DUT_TDO
JTAG
(CoreSight 10)
DUT_TJTAG_EN
DUT_PORESET
SDA_TCK
SDA_TMS
SDA_TDI
SDA_TRST
SDA_TDO
JTAG
JTAG
(CoreSight 10)
1V8
GPIO
Delay
SDHC1_CD_B/
PWR_OK
UART1
JTAG
UART
POWER_OK
Ethernet
SGMII PHYs
VSEL/
GPIO_1[23]
Voltage
Translator
1.8V
3.3V
K20
Figure 2-3. FRDM-LS1012A reset architecture
Table 2-4
summarizes the reset activity.
Table 2-4. Reset activity
Reset Source
Reset Reason
Actions taken
Power ON
Initialization after a
power cycle.
All the onboard devices are reset after a power cycle. PLL
and clock circuitry initialize to the default configuration.
SW1
Reset switch
Resets LS1012A and other board peripherals. Enables the
BOOTLOADER mode on the K20 CMSISDAP.
Debugger reset (J9 and K20)
Reset from JTAG
debugger
No power cycle. All devices are reset.
RESET_REQ_B
Reset request from
LS1012A
All devices are reset. No power cycle.
The reset is asserted for about 240 ms after all power supplies are stable. This is to meet
the LS1012A 100 ms reset specification. Power failure after system operation also asserts
the reset to all the devices on the board. The FRDM-LS1012A supports options to change
the PORCFG through the resistor mount option. Mount the resistors to drive the
corresponding PORCFG as low in
Table 2-5
.
Table 2-5. Configuration signals
Configuration signal
Nets sampled
Components on board
Default state
CFG_RCW_SRC1
CLK_OUT
R50
DNP
Reset and configuration signals
QorIQ FRDM-LS1012A Board Reference Manual, Rev. 3, 12/2016
16
NXP Semiconductors