The following table explains the FRDM-LS1012A voltage regulation.
Table 2-3. FRDM-LS1012A Voltage Regulation
Power
Voltage
Device
Description
Core, VDD
0.9 V (3.5
A max)
VR5100 SW1
Powers the LS1012A SoC Core voltage
G1VDD
1.35 V (1.5
A max)
VR5100 SW3
Powers the LS1012A SoC DDR circuitry
VCC_VREF
0.675 V
VR5100 VREF LDO
XVDD
1.35 V
VR5100 SW3
Powers the LS1012A SoC SerDes I/O circuitry
AVDD_SD1_PLL1
AVDD_SD1_PLL2
SVDD
0.9 V
VR5100 SW1
TH_VDD
1.8 V (1.25
A max)
VR5100 SW2
Thermal monitor unit supply voltage
AVDD_CGA1
AVDD_PLAT
Core, Platform, DDR, and SerDes PLL's supply voltages
XOSC_VDD
OVDD supply for LS1012A crystal oscillator
OVDD
General I/O voltage
USB_SVDD
USB_SDVDD
0.9 V
VR5100 SW1
Powers the LS1012A SoC USB circuitry
USB_HVDD
3.3 V
MC34713
EVDD
3.3 V
MC34713
VCC_POVDD
1.8 V
VR5100 LDO1
Powers the LS1012A SFP fuse programming voltage
2.3 Reset and configuration signals
The reset sequence can be triggered from various sources.
Chapter 2 LS1012AFRDM Functional Description
QorIQ FRDM-LS1012A Board Reference Manual, Rev. 3, 12/2016
NXP Semiconductors
15