MDIO
MDC
Ethernet Controller
LS1012
3V3
3V3
PHY_RST1
SGMII
MDI_0_P/N
MDI_1_P/N
MDI_3_P/N
MDI_2_P/N
PMEB
INTB
PHYRSTB
DVDD_RG
DVDD33
4.7K
PHY
SUPPORT
MODE: SGMII
RJ-45
1Gbps
100Mbps
3V3
4.7K
1V
REG_OUT
AVDD10
DVDD10
AVDD33
0 ohm
#1
REALTEK RTL8211FS-CG
48-PIN QFN
Notes and Assumptions:
- MAC connected to Serdes lane B is the same MAC connected to the RGMII interface.
so RGMII and SGMII ( lane B) can not be use at a time.
- If the Serdes is configured for 2 SGMII interfaces, then the RGMII interface is unused
(tristated unless the pinmuxing control register is configured for functionality other than
EC1 RGMII).
S
E
R
D
E
S
L
a
n
e B
TX_P/N
RX_P/N
HSIP/N
HSOP/N
EM1_MDC
EM1_MDIO
X
Transfo rmer
Voltage
Translator
1.8V 3.3V
VSEL/
GPIO_1[13]
Figure 2-6. SGMII PHY2
Table 2-8. Hardware bootstrap settings for Ethernet PHYs
Setting
Description
PHY_AD[2:0] = 001
PHY Addr = 0b00010 (for SGMII PHY1)
PHY Addr = 0b00001 (for SGMII PHY2)
CFG_LDO[1:0] = 10
External power voltage selections for IO pads (1.8 V)
CFG_MODE[2:0] = 011
UTP > SGMII
Table continues on the next page...
Ethernet controller
QorIQ FRDM-LS1012A Board Reference Manual, Rev. 3, 12/2016
20
NXP Semiconductors