NXP Semiconductors QorIQ FRDM-LS1012A, Reference Manual, Page: 21 / 31

Table 2-8. Hardware bootstrap settings for Ethernet PHYs (continued)
Setting Description
TXDLY = 1 RGMII TXC clock skew = 2.0 ns (through Register setting #17.8)
RXDLY = 1 RGMII TXC clock skew = 2.0 ns
2.8 Audio interface
The FRDM-LS1012A board supports the audio interface using the SGTL5000 codec.
This codec connects with LS1012A on the SAI2 interface.
SAI2 supports full duplex audio and takes bit clock (TX and RX BCLK) and frame clock
(TX and RX SYNC) as input from SGTL5000. The SGTL5000 generates these clocks
based on a 25 MHz MCLK, which is fed from the CLKOUT of LS1012A. The
SGTL5000 control interface is I2C-based and can be accessed at the 0x0A address.
2.9 USB interface
The FRDM-LS1012A board supports:
• one SuperSpeed USB 2.0/3.0 port - configured as On-The-Go (OTG) with a Micro-
AB connector. Based on the OTG configuration, the PHY can either operate in Type-
A or Type-B mode
• a 2-pin header (J12) to provide 5 V at 1 A power supply to the USB 2.0/3.0 port
The following figure shows the USB 2.0/3.0 PHY architecture on the FRDM-LS1012A.
Chapter 2 LS1012AFRDM Functional Description
QorIQ FRDM-LS1012A Board Reference Manual, Rev. 3, 12/2016
NXP Semiconductors 21