NXP Semiconductors P89LPC9321 UM10310, User Manual

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User manual Rev. 01 — 1 December 2008 41 of 139
NXP Semiconductors
UM10310
P89LPC9321 User manual
7.3 Mode 2
Mode 2 configures the Timer register as an 8-bit Counter (TLn) with automatic reload, as
shown in
Figure 17 . Overflow from TLn not only sets TFn, but also reloads TLn with the
contents of THn, which must be preset by software. The reload leaves THn unchanged.
Mode 2 operation is the same for Timer 0 and Timer 1.
7.4 Mode 3
When Timer 1 is in Mode 3 it is stopped. The effect is the same as setting TR1 = 0.
Timer 0 in Mode 3 establishes TL0 and TH0 as two separate 8-bit counters. The logic for
Mode 3 on Timer 0 is shown in
Figure 18 . TL0 uses the Timer 0 control bits: T0C/T,
T0GATE, TR0, INT0, and TF0. TH0 is locked into a timer function (counting machine
cycles) and takes over the use of TR1 and TF1 from Timer 1. Thus, TH0 now controls the
‘Timer 1’ interrupt.
Mode 3 is provided for applications that require an extra 8-bit timer. With Timer 0 in Mode
3, an P89LPC9321 device can look like it has three Timer/Counters.
Note: When Timer 0 is in Mode 3, Timer 1 can be turned on and off by switching it into and
out of its own Mode 3. It can still be used by the serial port as a baud rate generator, or in
any application not requiring an interrupt.
7.5 Mode 6
In this mode, the corresponding timer can be changed to a PWM with a full period of 256
timer clocks (see
Figure 19 ). Its structure is similar to mode 2, except that:
•
TFn (n = 0 and 1 for Timers 0 and 1 respectively) is set and cleared in hardware;
•
The low period of the TFn is in THn, and should be between 1 and 254, and;
•
The high period of the TFn is always 256
−
THn.
•
Loading THn with 00h will force the Tx pin high, loading THn with FFh will force the Tx
pin low.
Note that interrupt can still be enabled on the low to high transition of TFn, and that TFn
can still be cleared in software like in any other modes.
Table 28. Timer/Counter Control register (TCON) - address 88h) bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
Reset 0 0 0 0 0 0 0 0
Table 29. Timer/Counter Control register (TCON - address 88h) bit description
Bit Symbol Description
0 IT0 Interrupt 0 Type control bit. Set/cleared by software to specify falling edge/low level triggered external
interrupts.
1 IE0 Interrupt 0 Edge flag. Set by hardware when external interrupt 0 edge is detected. Cleared by hardware
when the interrupt is processed, or by software.
2 IT1 Interrupt 1 Type control bit. Set/cleared by software to specify falling edge/low level triggered external
interrupts.