UM10310_1
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 01 — 1 December 2008
57 of 139
NXP Semiconductors
UM10310
P89LPC9321 User manual
Fig 25. Capture/compare unit interrupts.
002aaa896
interrupt to
CPU
TOIE2 (TICR2.7)
TOIF2 (TIFR2.7)
TICIE2A (TICR2.0)
TICF2A (TIFR2.0)
TICIE2B (TICR2.1)
TICF2B (TIFR2.1)
TOCIE2A (TICR2.3)
TOCF2A (TIFR2.3)
TOCIE2B (TICR2.4)
TOCF2B (TIFR2.4)
TOCIE2C (TICR2.5)
TOCF2C (TIFR2.5)
TOCIE2D (TICR2.6)
TOCF2D (TIFR2.6)
EA (IEN0.7)
ECCU (IEN1.4)
PRIORITY
ENCODER
other
interrupt
sources
ENCINT.0
ENCINT.1
ENCINT.2
Table 45.
CCU interrupt status encode register (TISE2 - address DEh) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
-
-
-
-
-
ENCINT.2
ENCINT.1
ENCINT.0
Reset
x
x
x
x
x
0
0
0
Table 46.
CCU interrupt status encode register (TISE2 - address DEh) bit description
Bit Symbol
Description
2:0 ENCINT.2:0
CCU Interrupt Encode output. When multiple interrupts happen, more than one interrupt flag is set in
CCU Interrupt Flag Register (TIFR2). The encoder output can be read to determine which interrupt is
to be serviced. The user must write a logic 0 to clear the corresponding interrupt flag bit in the TIFR2
register after the corresponding interrupt has been serviced. Refer to
for TIFR2 description.
000 —
No interrupt pending.
001 —
Output Compare Event D interrupt (lowest priority)
010 —
Output Compare Event C interrupt.
011 —
Output Compare Event B interrupt.
100 —
Output Compare Event A interrupt.
101 —
Input Capture Event B interrupt.
110 —
Input Capture Event A interrupt.
111 —
CCU Timer Overflow interrupt (highest priority).
3:7 -
Reserved.
