UM10310_1
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 01 — 1 December 2008
23 of 139
NXP Semiconductors
UM10310
P89LPC9321 User manual
2.6 Watchdog oscillator option
The watchdog has a separate oscillator which has a frequency of 400 kHz, calibrated to
±
5 % at room temperature. This oscillator can be used to save power when a high clock
frequency is not needed.
2.7 External clock input option
In this configuration, the processor clock is derived from an external source driving the
XTAL1 / P3.1 pin. The rate may be from 0 Hz up to 18 MHz. The XTAL2 / P3.0 pin may be
used as a standard port pin or a clock output. When using an oscillator frequency above
12 Mhz, BOE1 bit (UCFG1.5) and BOE0 bit (UCFG1.3) are required to hold the device in
reset at power-up until V
DD
has reached its specified level.
Table 6.
On-chip RC oscillator trim register (TRIM - address 96h) bit description
Bit
Symbol
Description
0
TRIM.0
Trim value. Determines the frequency of the internal RC oscillator. During reset,
these bits are loaded with a stored factory calibration value. When writing to either
bit 6 or bit 7 of this register, care should be taken to preserve the current TRIM value
by reading this register, modifying bits 6 or 7 as required, and writing the result to
this register.
1
TRIM.1
2
TRIM.2
3
TRIM.3
4
TRIM.4
5
TRIM.5
6
ENCLK
when = 1,
CCLK
⁄
2
is output on the XTAL2 pin provided the crystal oscillator is not
being used.
7
RCCLK
when = 1, selects the RC Oscillator output as the CPU clock (CCLK). This allows for
fast switching between any clock source and the internal RC oscillator without
needing to go through a reset cycle.
Note: The oscillator must be configured in one of the following modes: Low frequency crystal,
medium frequency crystal, or high frequency crystal.
(1) A series resistor may be required to limit crystal drive levels. This is especially important for low
frequency crystals (see text).
Fig 7.
Using the crystal oscillator.
002aad364
XTAL1
XTAL2
quartz crystal or
ceramic resonator
(1)
