UM10310_1
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 01 — 1 December 2008
25 of 139
NXP Semiconductors
UM10310
P89LPC9321 User manual
2.9 Oscillator Clock (OSCCLK) wake-up delay
The P89LPC9321 has an internal wake-up timer that delays the clock until it stabilizes
depending on the clock source used. If the clock source is any of the three crystal
selections (low, medium and high frequencies) the delay is 1024 OSCCLK cycles plus
60
μ
s to 100
μ
s. If the clock source is the internal RC oscillator, the delay is
200
μ
s to 300
μ
s. If the clock source is watchdog oscillator or external clock, the delay is
32 OSCCLK cycles.
2.10 CPU Clock (CCLK) modification: DIVM register
The OSCCLK frequency can be divided down, by an integer, up to 510 times by
configuring a dividing register, DIVM, to provide CCLK. This produces the CCLK
frequency using the following formula:
CCLK frequency = f
osc
/ (2N)
Where: f
osc
is the frequency of OSCCLK, N is the value of DIVM.
Since N ranges from 0 to 255, the CCLK frequency can be in the range of f
osc
to f
osc
/510.
(for N = 0, CCLK = f
osc
).
This feature makes it possible to temporarily run the CPU at a lower rate, reducing power
consumption. By dividing the clock, the CPU can retain the ability to respond to events
other than those that can cause interrupts (i.e. events that allow exiting the Idle mode) by
executing its normal program at a lower rate. This can often result in lower power
consumption than in Idle mode. This can allow bypassing the oscillator start-up time in
cases where Power-down mode would otherwise be used. The value of DIVM may be
changed by the program at any time without interrupting code execution.
2.11 Low power select
The P89LPC9321 is designed to run at 18 MHz (CCLK) maximum. However, if CCLK is
8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to a logic 1 to lower the power
consumption further. On any reset, CLKLP is logic 0 allowing highest performance. This
bit can then be set in software if CCLK is running at 8 MHz or slower.
3.
Interrupts
The P89LPC9321 uses a four priority level interrupt structure. This allows great flexibility
in controlling the handling of the P89LPC9321’s 15 interrupt sources.
Table 9.
Oscillator type selection for clock switch
FOSC[2:0] Oscillator configuration
111
External clock input on XTAL1.
100
Watchdog Oscillator, 400 kHz ± 5 %.
011
Internal RC oscillator, 7.373 MHz ± 1 %.
010
Low frequency crystal, 20 kHz to 100 kHz.
001
Medium frequency crystal or resonator, 100 kHz to 4 MHz.
000
High frequency crystal or resonator, 4 MHz to 18 MHz.
