UM10413
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© NXP B.V. 2011. All rights reserved.
User manual
Rev. 1 — 16 December 2011
92 of 268
NXP Semiconductors
UM10413
MPT612 User manual
The UART0 Baud Rate Generator block, U0BRG, generates the timing enables used by
the UART0 TX block. The U0BRG clock input source is the APB clock (PCLK). The main
clock is divided down per the divisor specified in registers U0DLL and U0DLM and is a
16
oversample clock, NBAUDOUT.
The interrupt interface contains registers U0IER and U0IIR. The interrupt interface
receives several one clock-wide enables from the U0TX and U0RX blocks.
Status information from the U0TX and U0RX is stored in the U0LSR. Control information
for the U0TX and U0RX is stored in the U0LCR.