UM10413
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© NXP B.V. 2011. All rights reserved.
User manual
Rev. 1 — 16 December 2011
74 of 268
NXP Semiconductors
UM10413
MPT612 User manual
13.5.2 Example 2: an immediate output of 0s and 1s on a GPIO port
A write access to pins IOSET followed by a write to register IOCLR results in pins
outputting 0s slightly later than pins outputting 1s. There are systems that can tolerate this
delay of a valid output, but for some applications simultaneous output of a binary content
(mixed 0s and 1s) within a group of pins on a single GPIO port is required. This can be
accomplished by writing to the pins register IOPIN.
The following code preserves existing output on pins PIO[31:16] and PIO[7:0] and at the
same time sets PIO[15:8] to 0xA5, regardless of the previous value of pins PIO[15:8]:
IO0PIN = (IO0PIN && 0xFFFF00FF) || 0x0000A500
The same outcome can be obtained using the fast pin access.
Solution 1:
using 32-bit (word) accessible fast GPIO registers
FIO0MASK = 0xFFFF00FF;
FIO0PIN = 0x0000A500;
Solution 2:
using 16-bit (half-word) accessible fast GPIO registers
FIO0MASKL = 0x00FF;
FIO0PINL = 0xA500;
Solution 3:
using 8-bit (byte) accessible fast GPIO registers
FIO0PIN1 = 0xA5;
13.5.3 Writing to IOSET/IOCLR vs. IOPIN
A write to register IOSET/IOCLR allows easy change of the pin’s selected output pin(s) to
HIGH/LOW level at a time. Only pin/bit(s) in the IOSET/IOCLR written with logic 1 is set to
HIGH/LOW level, while pin/bit(s) written with logic 0 remain unaffected. However, by just
writing to either IOSET or IOCLR register it is not possible to output arbitrary binary data
containing a mixture of 0s and 1s on a GPIO pin instantaneously.
A write to register IOPIN enables instantaneous output of a desired content on the parallel
GPIO. Binary data written into register IOPIN affects all output configured pins of that
parallel port: 0s in IOPIN produces LOW level pin outputs, and 1s in IOPIN produces
HIGH level pin outputs. In order to change the output of only a group of pins, the
application must logically AND readout from the IOPIN with the mask containing 0s in bits
corresponding to pins that will be changed, and 1s for all others. Finally, this result has to
be logically ORred with the desired content and stored back into register IOPIN. Example
2 above illustrates the output of 0xA5 on pins 15 to 8 while preserving all other output pins
as they were before.
13.5.4 Output signal frequency considerations when using slow speed GPIO and
enhanced GPIO registers
The enhanced features of the fast GPIO pins available on this MPT612 make GPIO pins
more responsive to code that has the task of controlling them. In particular, software
access to a GPIO pin is 3.5 times faster via the fast GPIO registers than it is when a set of
slow speed registers is used. As a result of the increased access speed, the maximum
output frequency of the digital pin is also increased 3.5 times. This large increase in output