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UM10413

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© NXP B.V. 2011. All rights reserved.

User manual

Rev. 1 — 16 December 2011 

31 of 268

NXP Semiconductors

UM10413

MPT612 User manual

entered due to an IRQ being received when executing the MSR instruction which disables 
IRQs, then bit I is set in SPSR. The routine therefore assumes that it could not have been 
entered via an IRQ.

Problem 2:

 FIQs and IRQs are both disabled by the same write to the CPSR. In this case, 

if an IRQ is received during the CPSR write, FIQs are disabled for the execution time of 
the IRQ handler. This arrangement cannot be acceptable in a system where FIQs must 
not be disabled for more than a few cycles.

9.6.2 Workaround

There are 3 suggested workarounds. The one which is most applicable depends upon the 
requirements of the particular system.

9.6.3 Solution 1: Test for an IRQ received during a write to disable IRQs

Add code similar to the following at the start of the interrupt routine.

SUB      lr, lr, #4       ; Adjust LR to point to return

STMFD    sp!, {..., lr}   ; Get some free legs

MRS      lr, SPSR         ; See if we got an interrupt while

TST      lr, #I_Bit       ; interrupts were disabled.

LDMNEFD  sp!, {..., pc}^  ; If so, just return immediately.

                          ; The interrupt remains pending since we have not

                          ; acknowledged it and is reissued when interrupts

                          ; are next enabled.

                          ; Rest of interrupt routine

This code tests for the situation where the IRQ was received during a write to disable 
IRQs. If so, the code returns immediately - resulting in the IRQ not being acknowledged 
(cleared), and further IRQs being disabled.

In order to resolve the first issue, similar code can also be applied to the FIQ handler.

This method is the recommended workaround, as it overcomes both problems mentioned 
previously. However, in the case of problem two, it does add several cycles to the 
maximum length of time FIQs are disabled.

9.6.4 Solution 2: Disable IRQs and FIQs using separate writes to the CPSR

MRS  r0, cpsr

ORR  r0, r0, #I_Bit   ;disable IRQs

MSR  cpsr_c, r0

ORR  r0, r0, #F_Bit   ;disable FIQs

MSR  cpsr_c, r0

This arrangement is the best workaround where the maximum time for which FIQs are 
disabled is critical (it does not increase this time at all). However, it does not solve problem 
one, and requires extra instructions at every point where IRQs and FIQs are disabled 
together.

9.6.5 Solution 3: Re-enable FIQs at the beginning of the IRQ handler

As the required state of all bits in the CPSR c field are known, this solution is efficiently 
achieved by writing an immediate value to CPSR_C, for example:

Summary of Contents for MPT612

Page 1: ...ember 2011 User manual Document information Info Content Keywords ARM ARM7 embedded 32 bit MPPT MPT612 Abstract This document describes all aspects of the MPT612 an IC designed for applications using solar photovoltaic PV cells or fuel cells ...

Page 2: ...reserved User manual Rev 1 16 December 2011 2 of 268 Contact information For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com NXP Semiconductors UM10413 MPT612 User manual Revision history Rev Date Description 1 20111216 initial version ...

Page 3: ... sensors The IC dynamically extracts the maximum power from the PV panel without user intervention when enabled The IC can be configured for boundary conditions set in software There is up to 15 kB of flash memory available for application software In this user manual solar PV terminology is primarily used as an example However the MPT612 is equally useful for fuel cells or any other DC source whi...

Page 4: ...6 bytes in 1 ms 3 Applications Battery charge controller for solar PV power and fuel cells The use cases are Battery charging for home appliances such as lighting DC fans DC TV DC motors or any other DC appliance Battery charging for public lighting and signaling such as LED street lighting garden driveway lighting dusk to dawn lighting railway signaling traffic signaling remote telecom terminals ...

Page 5: ...on is being executed its successor is being decoded and a third instruction is being read from memory The ARM7TDMI S processor also employs a unique architectural strategy known as Thumb making it suitable for high volume applications with memory restrictions or applications where code density is an issue The key idea behind Thumb is a super reduced instruction set Essentially the ARM7TDMI S proce...

Page 6: ...r data storage The SRAM can be accessed as 8 bit 16 bit and 32 bit The MPT612 provides 8 kB of static RAM 6 Block diagram Fig 1 MPT612 block diagram 001aam089 PV VOLTAGE MEASUREMENT PV voltage sense PV CURRENT MEASUREMENT PV current sense BATTERY VOLTAGE MEASUREMENT battery voltage sense BATTERY CURRENT MEASUREMENT battery current sense TEMPERATURE MEASUREMENT temperature sense LOAD CURRENT MEASUR...

Page 7: ...ire address space from the user program viewpoint following reset The interrupt vector area supports address remapping which is described later in this section Fig 2 System memory map aaa 000568 0 0 GB 1 0 GB 0x0000 0000 RESERVED ADDRESS SPACE 8 kB ON CHIP STATIC RAM RESERVED ADDRESS SPACE 0x4000 2000 0x4000 1FFF 0x4000 0000 2 0 GB 0x8000 0000 BOOT BLOCK 0x7FFF E000 0x7FFF DFFF 3 0 GB 0xC000 0000 ...

Page 8: ...erals Each peripheral space is 16 kB in size simplifying address decoding for each peripheral All peripheral register addresses are word aligned to 32 bit boundaries regardless of their size eliminating the need for byte lane mapping hardware to allow byte AHB section is 128 16 kB blocks totaling 2 MB APB section is 128 16 kB blocks totaling 2 MB Fig 3 Peripheral memory map aaa 000569 RESERVED RES...

Page 9: ... requires all word and half word registers to be accessed at once For example it is not possible to read or write the upper byte of a word register separately Fig 4 AHB peripheral map aaa 000570 VECTORED INTERRUPT CONTROLLER AHB PERIPHERAL 0 0xFFFF F000 4G 4K 0xFFFF C000 0xFFFF 8000 AHB PERIPHERAL 125 AHB PERIPHERAL 124 AHB PERIPHERAL 3 AHB PERIPHERAL 2 AHB PERIPHERAL 1 AHB PERIPHERAL 126 0xFFFF 4...

Page 10: ... boot block and SRAM spaces need remapping to allow alternative uses of interrupts in the different operating modes described in Table 4 Remapping of the interrupts is accomplished via the memory mapping control feature Section 10 7 Memory mapping control on page 42 Table 2 APB peripheries and base addresses APB peripheral Base address Peripheral name 0 0xE000 0000 Watchdog timer 1 0xE000 4000 res...

Page 11: ...rupt handlers There are three reasons this configuration was chosen To give the FIQ handler in the flash memory the advantage of not having to take a memory boundary caused by the remapping into account Minimize the need for the SRAM and boot block vectors to deal with arbitrary boundaries in the middle of code space Table 3 ARM exception vector locations Address Exception 0x0000 0000 reset 0x0000...

Page 12: ... ARM derivative For the MPT612 Address space between on chip Non Volatile Memory and on chip SRAM labeled Reserved Address Space in Figure 2 For this device memory address range is from 0x0000 8000 to 0x3FFF FFFF Address space between on chip static RAM and the boot block Labeled Reserved Address Space in Figure 2 For this device memory address range is from 0x4000 2000 to 0x7FFF DFFF Address spac...

Page 13: ...s used on predecessor devices It includes three 128 bit buffers called the prefetch buffer the branch trail buffer and the data buffer The ARM is stalled while a fetch is initiated for the 128 bit line for an Instruction Fetch not satisfied by either the prefetch or branch trail buffer or a prefetch not initiated for that line If a prefetch is initiated but not yet completed the ARM is stalled for...

Page 14: ...here are no further instruction fetch delays until a new and different branch occurs 8 2 MAM blocks The MAM is divided into several functional blocks A flash address latch and an incrementing function to form prefetch addresses A 128 bit prefetch buffer and an associated address latch and comparator A 128 bit branch trail buffer and an associated address latch and comparator A 128 bit data buffer ...

Page 15: ... memory does not allow access during programming and erase operations the MAM must force the CPU to wait if a memory access to a flash address is requested while the flash module is busy Under some conditions this delay can result in a watchdog time out You must ensure that an unwanted watchdog reset does not cause a system failure while programming or erasing the flash memory To preclude the poss...

Page 16: ...on This method saves power while resulting in the same execution timing The MAM can truly be turned off by setting the fetch timing value in MAMTIM to one clock 8 4 MAM configuration After reset the MAM defaults to the disabled state Software can turn memory access acceleration on or off at any time This method allows most of an application to be run at the highest possible performance while certa...

Page 17: ...ing MAM timing to match the processor operating frequency Flash access times from 1 clock to 7 clocks are possible Single clock flash accesses removes the MAM from timing calculations In this case the MAM mode can be selected to optimize power usage Table 7 Summary of MAM registers Name Description Access Reset value 1 Address MAMCR MAM control register Determines MAM functional mode to what exten...

Page 18: ...ectored IRQ interrupts 16 priority levels dynamically assigned to interrupt requests Software interrupt generation Table 9 MAM Timing register MAMTIM address 0xE01F C004 bit description Bit Symbol Value Description Reset value 2 0 MAM_fetch_ cycle_timing 000 0 reserved 07 001 1 MAM fetch cycles are 1 processor clock CCLK in duration 010 2 MAM fetch cycles are 2 CCLKs in duration 011 3 MAM fetch cy...

Page 19: ... IRQ is requesting the VIC provides the address of the highest priority requesting IRQ service routine otherwise it provides the address of a default routine shared by all the non vectored IRQs The default routine can read another VIC register to see what IRQs are active All registers in the VIC are word registers Byte and halfword read write are not supported Additional information on the Vectore...

Page 20: ...Addr7 vector address 7 register R W 0 0xFFFF F11C VICVectAddr8 vector address 8 register R W 0 0xFFFF F120 VICVectAddr9 vector address 9 register R W 0 0xFFFF F124 VICVectAddr10 vector address 10 register R W 0 0xFFFF F128 VICVectAddr11 vector address 11 register R W 0 0xFFFF F12C VICVectAddr12 vector address 12 register R W 0 0xFFFF F130 VICVectAddr13 vector address 13 register R W 0 0xFFFF F134 ...

Page 21: ...egister without having to read it first VICVectCntl13 vector control 13 register R W 0 0xFFFF F234 VICVectCntl14 vector control 14 register R W 0 0xFFFF F238 VICVectCntl15 vector control 15 register R W 0 0xFFFF F23C Table 11 VIC register map continued Name Description Access Reset value 1 Address Table 12 Software interrupt register VICSoftInt address 0xFFFF F018 bit allocation Reset value 0x0000...

Page 22: ...SPI0 I2C0 Access WO WO WO WO WO WO WO WO Bit 7 6 5 4 3 2 1 0 Symbol UART1 UART0 TIMER1 reserved ARMCore1 ARMCore0 WDT Access WO WO WO WO WO WO WO WO Table 15 Software interrupt clear register VICSoftIntClear address 0xFFFF F01C bit description Bit Symbol Value Description Reset value 31 0 see Table 14 0 writing logic 0 leaves corresponding bit in VICSoftInt unchanged 0 1 writing logic 1 clears cor...

Page 23: ...bit number 0 1 asserts hardware or software interrupt request with this bit number Table 18 Interrupt enable register VICIntEnable address 0xFFFF F010 bit allocation Reset value 0x0000 0000 Bit 31 30 29 28 27 26 25 24 Symbol TIMER3 reserved Access R W R W R W R W R W R W R W R W Bit 23 22 21 20 19 18 17 16 Symbol I2C1 AD0 EINT2 Access R W R W R W R W R W R W R W R W Bit 15 14 13 12 11 10 9 8 Symbo...

Page 24: ...O WO Bit 7 6 5 4 3 2 1 0 Symbol UART1 UART0 TIMER1 reserved ARMCore1 ARMCore0 WDT Access WO WO WO WO WO WO WO WO Table 21 Software interrupt clear register VICIntEnClear address 0xFFFF F014 bit description Bit Symbol Value Description Reset value 31 0 see Table 20 0 writing logic 0 leaves corresponding bit in VICIntEnable unchanged 0 1 writing logic 1 clears corresponding bit in interrupt enable r...

Page 25: ...egister VICIntSelect address 0xFFFF F00C bit description Bit Symbol Value Description Reset value 31 0 see Table 22 0 assigns interrupt request with this bit number to IRQ category 0 1 assigns interrupt request with this bit number to FIQ category Table 24 IRQ Status register VICIRQStatus address 0xFFFF F000 bit allocation Reset value 0x0000 0000 Bit 31 30 29 28 27 26 25 24 Symbol TIMER3 reserved ...

Page 26: ... RO RO Bit 15 14 13 12 11 10 9 8 Symbol EINT1 EINT0 RTC PLL SSP SPI1 SPI0 I2C0 0 Access RO RO RO RO RO RO RO RO Bit 7 6 5 4 3 2 1 0 Symbol UART1 UART0 TIMER1 reserved ARMCore1 ARMCore0 WDT Access RO RO RO RO RO RO RO RO Table 27 FIQ Status register VICFIQStatus address 0xFFFF F004 bit description Bit Symbol Description Reset value 31 0 see Table 26 a bit read as logic 1 indicates a corresponding i...

Page 27: ...sserted and assigned to an enabled vectored IRQ slot the value from this register is used for the highest priority slot and is provided when IRQ service routine reads vector address register VICVectAddr see Section 9 4 10 0x0000 0000 Table 30 Default vector address register VICDefVectAddr address 0xFFFF F034 bit description Bit Symbol Description Reset value 31 0 IRQ_vector if an IRQ service routi...

Page 28: ...e out Indicator CTI 6 0x0000 0040 UART1 Rx Line Status RLS Transmit Holding Register Empty THRE Rx Data Available RDA Character Time out Indicator CTI Modem Status Interrupt MSI 7 0x0000 0080 reserved 8 0x0000 0100 I2C0 SI state change 9 0x0000 0200 SPI0 SPI0 Interrupt Flag SPI0F Mode Fault MODF 10 0x0000 0400 SPI1 SSP Tx FIFO at least half empty TXRIS Rx FIFO at least half full RXRIS Receive Time...

Page 29: ...t the interrupt that triggered the sequence starting with step 1 is no longer pending interrupt got disabled in the executed code In this case the VIC is not able to identify clearly the interrupt that generated the interrupt request and as a result the VIC returns the default interrupt VicDefVectAddr 0xFFFF F034 This potentially disastrous chain of events can be prevented in two ways Fig 7 Block ...

Page 30: ...ommitted to taking the interrupt exception before bit I was set in the CPSR 4 The CPSR with bit I and bit F set is moved to the SPSR_IRQ This means that on entry to the IRQ interrupt service routine you can see the unusual effect that an IRQ interrupt has been taken while bit I in SPSR is set In the example above bit F is also set in both CPSR and SPSR This means that FIQs are disabled upon entry ...

Page 31: ...NEFD sp pc If so just return immediately The interrupt remains pending since we have not acknowledged it and is reissued when interrupts are next enabled Rest of interrupt routine This code tests for the situation where the IRQ was received during a write to disable IRQs If so the code returns immediately resulting in the IRQ not being acknowledged cleared and further IRQs being disabled In order ...

Page 32: ...terrupt source as FIQ increases the interrupt latency Following the completion of the desired interrupt service routine clearing of the interrupt flag on the peripheral level propagates corresponding bits in VIC registers VICRawIntr VICFIQStatus and VICIRQStatus Also before the next interrupt can be serviced it is necessary that write is performed into register VICVectAddr before the return from i...

Page 33: ...llowing instruction can be placed at 0x0000 0018 LDR pc pc 0xFF0 This instruction loads PC with the address that is present in register VICVectAddr In case UART0 request is made VICVectAddr is identical to VICVectAddr0 while in case SPI0 request is made the value from VICVectAddr1 is found here If either UART0 or SPI0 have not generated an IRQ request but UART1 and or I2C are the reason the conten...

Page 34: ...nal hardware request to start ISP command handler see Section 25 5 Description on page 217 for more details on ISP and serial boot loader EINT2 input external interrupt input 2 see EINT0 description pin PIO15 can be selected to perform EINT2 function RESET input external reset input a LOW on this pin resets the chip changing I O ports and peripherals to their default states and processor to start ...

Page 35: ...le the input clock signal with a capacitor of 100 pF CC in Figure 8 drawing a with an amplitude of at least 200 mV RMS Pin XTAL2 in this configuration can be left unconnected If slave mode is selected the fosc signal of 50 to 50 duty cycle can range from 1 MHz to 25 MHz External components and models used in oscillation mode are shown in Figure 8 drawings b and c and in Table 36 Since the feedback...

Page 36: ...612 Table 36 Recommended values for CX1 X2 in oscillation mode crystal and external components parameters Fundamental oscillation frequency fosc Crystal load capacitance CL Maximum crystal series resistance RS External load capacitors CX1 CX2 1 MHz to 5 MHz 10 pF n a n a 20 pF n a n a 30 pF 300 58 pF 58 pF 5 MHz to 10 MHz 10 pF 300 18 pF 18 pF 20 pF 300 38 pF 38 pF 30 pF 300 58 pF 58 pF 10 MHz to ...

Page 37: ...lose as possible to the chip oscillator input and output pins Take care that the load capacitors Cx1 and Cx2 and Cx3 in case of third overtone crystal usage have a common ground plane Connect the external components to the ground plain Make loops as small as possible to reduce the noise coupled in via the PCB as small as possible Parasitics must be as small as possible Start with small values for ...

Page 38: ...d EXTMODE sets its interrupt flag in this register This asserts the corresponding interrupt request to the VIC which causes an interrupt if interrupts from the pin are enabled Writing ones to bits EINT0 through EINT2 in register EXTINT clears the corresponding bits In level sensitive mode this action is efficacious only when the pin is in its inactive state Once a bit from EINT0 to EINT2 is set an...

Page 39: ...ister EXTINT address 0xE01F C140 bit description Bit Symbol Description Reset value 0 EINT0 in level sensitive mode this bit is set if EINT0 function is selected for its pin and pin is in its active state In edge sensitive mode this bit is set if EINT0 function is selected for its pin and the selected edge occurs on the pin cleared by writing a logic 1 to it except in level sensitive mode when pin...

Page 40: ...mode 10 5 5 External interrupt polarity register EXTPOLAR 0xE01F C14C In level sensitive mode the bits in this register select whether the corresponding pin is high or low active In edge sensitive mode they select whether the pin is rising or falling edge sensitive Only pins that are selected for the EINT function see Section 12 4 Table 39 Interrupt wake up register INTWAKE address 0xE01F C144 bit...

Page 41: ...fore enabling initializing or re enabling the interrupt to clear bit EXTINT that might be set by changing the polarity Table 41 External interrupt polarity register EXTPOLAR address 0xE01F C14C bit description Bit Symbol Value Description Reset value 0 EXTPOLAR0 0 EINT0 is low active or falling edge sensitive depending on EXTMODE0 0 1 EINT0 is high active or rising edge sensitive depending on EXTM...

Page 42: ...ding the wake up timer on page 54 Fig 11 External interrupt logic R S Q D Q S GLITCH FILTER wake up enable one bit of EXTWAKE APB Read of EXTWAKE EINTi to wake up timer 1 PCLK PCLK interrupt flag one bit of EXTINT APB read of EXTINT to VIC 1 EINTi APB Bus Data EXTMODEi reset write 1 to EXTINTi EXTPOLARi R S Q PCLK D Q aaa 000576 Table 42 System control and status flags register SCS address 0xE01F ...

Page 43: ...sing a Current Controlled Oscillator CCO The multiplier can be an integer from 1 to 32 in practice the multiplier value cannot be higher than 6 on the MPT612 due to the upper frequency limit of the CPU The CCO operates in the range 156 MHz to 320 MHz so there is an additional divider in the loop to keep the CCO within its frequency range while the PLL is providing the desired output frequency The ...

Page 44: ...Reset value reflects the data stored in used bits only It does not include the content of reserved bits Table 44 PLL registers Generic name Description Access Reset value 1 Address PLLCON PLL control register Holding register for updating PLL control bits Values written to this register do not take effect until a valid PLL feed sequence occurs R W 0 0xE01F C080 PLLCFG PLL configuration register Ho...

Page 45: ...LLFEED 0xE01F C08C on page 47 and Section 10 8 3 Fig 12 PLL block diagram aaa 000577 CD 2P CLOCK SYNCHRONIZATION PD CCLK PLLC PLOCK fosc PLLE PHASE FREQUENCY DETECTOR bypass MSEL 4 0 CD MSEL 4 0 fout DIV BY M CCO fcco 0 0 PSEL 1 0 direct 0 1 PD PD 0 1 1 0 Table 45 PLL control register PLLCON address 0xE01F C080 bit description Bit Symbol Description Reset value 0 PLLE PLL enable If logic 1 and aft...

Page 46: ... register PLLSTAT provides the actual PLL parameters that are in effect at the time it is read as well as the PLL status PLLSTAT can disagree with values found in PLLCON and PLLCFG because changes to those registers do not take effect until a proper PLL feed has occurred see Section 10 8 7 Table 46 PLL configuration register PLLCFG address 0xE01F C084 bit description Bit Symbol Description Reset v...

Page 47: ...cles The latter requirement implies that interrupts must be disabled for the duration of the PLL feed operation If either of the feed values is incorrect or one of the previously mentioned conditions is not met any changes to register PLLCON or PLLCFG are not effective 9 PLLC read back for bit PLL Connect When PLLC and PLLE are both logic 1 the PLL is connected as the clock source for the MPT612 W...

Page 48: ... fosc is in the range 10 MHz to 25 MHz CCLK is in the range 10 MHz to fmax the maximum allowed frequency for the MPT612 embedded in and determined by the system MPT612 fCCO is in the range 156 MHz to 320 MHz 10 8 10 Procedure for determining PLL settings If a particular application uses the PLL its configuration can be determined as follows 1 Choose the desired processor operating frequency CCLK T...

Page 49: ...uently M 1 5 is written as PLLCFG 4 0 Value for P can be derived from P fCCO CCLK 2 using condition that fCCO must be in the range 156 MHz to 320 MHz Assuming the lowest allowed frequency for fCCO 156 MHz P 156 MHz 2 60 MHz 1 3 The highest fCCO frequency criteria produces P 2 67 The only solution for P that satisfies both of these requirements and is listed in Table 51 is P 2 Therefore PLLCFG 6 5 ...

Page 50: ...Section 24 6 14 Power control register group on page 210 In Deep power down mode all power is removed from the internal chip logic except for the RTC module the I O ports the SRAM and the 32 kHz external oscillator For additional power savings SRAM and the 32 kHz oscillator can be powered down individually The Deep power down mode produces the lowest possible power consumption without actually rem...

Page 51: ...register is possible only if the peripheral is enabled in register PCONP Table 54 Power control register PCON address 0xE01F COCO bit description Bit Symbol Description Reset value 0 IDL Idle mode If logic 1 causes processor clock to stop while on chip peripherals remain active Any enabled interrupt from a peripheral or an external interrupt source causes processor to resume execution 0 1 PD Power...

Page 52: ...e oscillator and the wake up timer are shown in Figure 13 The reset logic is shown in Figure 14 The reset glitch filter allows the processor to ignore external reset pulses that are short and also determines the minimum duration of RESET that must be asserted in order to guarantee a chip reset Once asserted pin RESET can be deasserted only when the crystal oscillator is fully running and an adequa...

Page 53: ...page 217 examines the on chip bootloader when this code is executed after every reset It is possible for a chip reset to occur during a Flash programming or erase operation The Flash memory interrupts the ongoing operation and holds off the completion of reset to the CPU until internal Flash high voltages have settled 1 Reset time The reset time must be held LOW This time depends on system paramet...

Page 54: ...ernal reset START COUNT2n oscillator output fosc reset to the on chip circuitry reset to PCON PD write 1 from APB Reset EINT0 wake up EINT1 wake up EINT2 wake up PLL Table 56 Reset source identification register RSIR address 0xE01F C180 bit description Bit Symbol Description Reset value 0 POR Power On Reset POR event sets this bit and clears all other bits in this register If another reset signal ...

Page 55: ...on page 56 Because the APB Divider is connected to the PLL output the PLL remains active if it was running during Idle mode 10 11 1 Register description Only one register is used to control the APB Divider 1 Reset value reflects the data stored in used bits only It does not include the content of reserved bits 10 11 2 APBDIV register APBDIV 0xE01F C100 Register APB Divider contains 2 bits allowing...

Page 56: ...conditions Once a clock is detected the wake up timer counts 4096 clocks then enables the on chip circuitry to initialize When the on board module s initialization is complete the processor is released to execute instructions if the external reset is de asserted In the case where an external clock source is used in the system as opposed to a crystal connected to the oscillator pins the possibility...

Page 57: ...r it can be debugged or protected from observation Details on the way Code Read Protection works can be found in Section 25 8 Code Read Protection CRP on page 223 11 Pin configuration 11 1 Pinout Fig 16 LQFP48 pin configuration MPT612FBD48 PIO19 MAT1_2 MISO1 PIO11 CTS1 CAP1_1 AD4 PIO20 MAT1_3 MOSI1 PIO10 RTS1 CAP1_0 AD3 PIO21 SSEL1 MAT3_0 PVCURRENTSENSE VDD RTC PVVOLTSENSEBOOST VDDC PVVOLTSENSEBUC...

Page 58: ... O SDA0 I2C0 data input output open drain output for I2C bus compliance PIO4 SCK0 22 1 I O PIO4 general purpose input output digital pin I O SCK0 serial clock for SPI0 SPI clock output from master or input to slave PIO5 MISO0 23 1 I O PIO5 general purpose input output digital pin I O MISO0 master in slave out for SPI0 Data input to SPI master or data output from SPI slave PIO6 MOSI0 24 1 I O PIO6 ...

Page 59: ...1 I2C1 clock input output This pin is an open drain output if I2C1 function is selected in the pin connect block PIO18 CAP1_3 SDA1 48 6 I O PIO18 general purpose input output digital pin The output is not open drain I CAP1_3 capture input for timer 1 channel 3 I O SDA1 I2C1 data input output This pin is an open drain output if I2C1 function is selected in the pin connect block PIO19 MAT1_2 MISO1 1...

Page 60: ...O MAT3_3 PWM output 3 for timer 3 PIO31 TDO 16 1 O PIO31 general purpose output only digital pin O TDO test data out for JTAG interface If JTAGSEL is HIGH this pin is automatically configured for use with EmbeddedICE Debug mode RTCX1 20 7 8 I input to RTC oscillator circuit input voltage must not exceed 1 8 V RTCX2 25 7 8 O output from RTC oscillator circuit RTCK 26 7 I O Returned test clock outpu...

Page 61: ...VDD IO and VDD ADC 3 0 V pad providing digital I O functions with TTL levels and hysteresis and 10 ns slew rate control If configured for an input function this pad utilizes a built in glitch filter that blocks pulses shorter than 3 ns 5 A LOW level during reset on pin PIO14 is considered as an external hardware request to start the ISP command handler 6 Open drain 5 V tolerant if VDD IO and VDD A...

Page 62: ...hat is currently selected for the port pin hosting the ADC input this ADC input can be read at any time and variations of the voltage level on this pin is reflected in the ADC readings However valid analog reading s can be obtained only if the function of an analog input is selected Only in this case the proper interface circuit is active between the physical pin and the ADC module In all other ca...

Page 63: ...rved 3 2 PIO1 00 GPIO pin 1 0 01 RXD0 UART0 10 MAT3 2 Timer 3 11 reserved 5 4 PIO2 00 GPIO pin 2 0 01 SCL0 I2C0 11 reserved 7 6 PIO3 00 GPIO pin 3 0 01 SDA0 I2C0 11 reserved 9 8 PIO4 00 GPIO pin 4 0 01 SCK0 SPI0 11 reserved 11 10 PIO5 00 GPIO pin 5 0 01 MISO0 SPI0 11 reserved 13 12 PIO6 00 GPIO pin 6 0 01 MOSI0 SPI0 11 reserved 15 14 PIO7 00 GPIO pin 7 0 01 SSEL0 SPI0 10 PWMOUT0 11 reserved 17 16 ...

Page 64: ...O pin 11 0 01 CTS1 UART1 10 CAP1 1 Timer 1 11 AD4 25 24 PIO12 00 GPIO pin 12 0 01 DSR1 UART1 10 MAT1 0 Timer 1 11 AD5 27 26 PIO13 00 GPIO pin 13 0 01 reserved 10 MAT1 1 Timer 1 11 DTR1 UART1 29 28 PIO14 00 GPIO pin 14 0 01 EINT1 10 SCK1 SSP1 11 DCD1 UART1 31 30 PIO15 00 GPIO pin 15 0 01 EINT2 10 reserved 11 RI1 UART1 Table 61 Pin function select register 0 PINSEL0 address 0xE002 C000 continued PIN...

Page 65: ...13 12 PIO22 00 GPIO pin 22 0 01 reserved 10 reserved 11 PVVOLTSENSEBUCK 15 14 PIO23 00 GPIO pin 23 0 01 reserved 10 reserved 11 PVVOLTSENSEBOOST 17 16 PIO24 00 GPIO pin 24 0 01 reserved 10 reserved 11 PVCURRENTSENSE 19 18 PIO25 00 GPIO pin 25 0 01 reserved 10 reserved 11 AD6 21 20 PIO26 00 GPIO pin 26 0 01 reserved 10 reserved 11 AD7 23 22 PIO27 00 GPIO pin 27 0 01 TRST JTAG 11 reserved 25 24 PIO2...

Page 66: ...ndependent sets of registers One set provides enhanced features and higher speed GPIO pin access The other register set provides slow speed GPIO pin access Enhanced GPIO functions GPIO registers are relocated to the ARM local bus to achieve the fastest possible I O timing Mask registers allow sets of port bits to be treated as a group leaving other bits unchanged All registers are byte and half wo...

Page 67: ...riting to individual pins of the GPIO port without the overhead of software masking The user must select in register System Control and Status flags SCS whether a GPIO will be accessed via registers that provide enhanced features or the set of slow speed GPIO registers see Section 10 6 1 System control and status flags register SCS 0xE01F C1A0 on page 42 While both fast and slow speed GPIO registe...

Page 68: ...ars corresponding bits in register IOSET Writing logic 0s has no effect WO 0x0000 0000 0xE002 800C IO0CLR Table 66 GPIO register map local bus accessible registers enhanced GPIO features Generic name Description Access Reset value 1 PORT0 address and name FIODIR fast GPIO direction control register Individually controls direction of each pin R W 0x0000 0000 0x3FFF C000 FIO0DIR FIOMASK fast mask re...

Page 69: ... 8008 bit description Bit Symbol Value Description Reset value 31 0 P0xDIR slow GPIO direction control bits Bit 0 controls PIO0 bit 30 controls PIO30 0x0000 0000 0 controlled pin is input 1 controlled pin is output Table 68 Fast GPIO direction register FIO0DIR address 0x3FFF C000 bit description Bit Symbol Value Description Reset value 31 0 FP0xDIR fast GPIO direction control bits Bit 0 in FIO0DIR...

Page 70: ...ue Use this feature carefully in an application since it affects all pins The slow speed GPIO register is the IO0PIN while the enhanced GPIOs are supported via register FIO0PIN Access to pins via register FIOPIN is conditioned by the corresponding register FIOMASK see Section 13 4 2 on page 69 Table 70 Fast GPIO mask register FIO0MASK address 0x3FFF C010 bit description Bit Symbol Value Descriptio...

Page 71: ...ported via register FIO0SET Access to pins via register FIOSET is conditioned by the corresponding register FIOMASK see Section 13 4 2 on page 69 Table 72 GPIO Pin value register IO0PIN address 0xE002 8000 bit description Bit Symbol Description Reset value 31 0 P0xVAL slow GPIO pin value bits Bit 0 in IO0PIN corresponds to PIO0 Bit 31 in IO0PIN corresponds to PIO31 n a Table 73 Fast GPIO pin value...

Page 72: ...ds to PIO0 Bit 31 in IO0SET corresponds to PIO31 0x0000 0000 Table 76 Fast GPIO output set register FIO0SET address 0x3FFF C018 bit description Bit Symbol Description Reset value 31 0 FP0xSET fast GPIO output value set bits Bit 0 in FIO0SET corresponds to PIO0 Bit 31 in FIO0SET corresponds to PIO31 0x0000 0000 Table 77 Fast GPIO port 0 output set byte and half word accessible register description ...

Page 73: ...llows on PIO7 write access to IO0SET and the final write to register IO0CLR sets pin PIO7 back to LOW level Table 79 Fast GPIO output clear register 0 FIO0CLR address 0x3FFF C01C bit description Bit Symbol Description Reset value 31 0 FP0xCLR fast GPIO output value clear bits Bit 0 in FIO0CLR corresponds to PIO0 Bit 31 in FIO0CLR corresponds to PIO31 0x0000 0000 Table 80 Fast GPIO output clear byt...

Page 74: ...n bit s in the IOSET IOCLR written with logic 1 is set to HIGH LOW level while pin bit s written with logic 0 remain unaffected However by just writing to either IOSET or IOCLR register it is not possible to output arbitrary binary data containing a mixture of 0s and 1s on a GPIO pin instantaneously A write to register IOPIN enables instantaneous output of a desired content on the parallel GPIO Bi...

Page 75: ... 8 MAM usage notes on page 18 Execution from the on chip SRAM is independent of the MAM setup set port 0 to slow GPIO ldr r0 0xe01fc1a0 register address SCS register mov r1 0x0 set bit 0 to 0 str r1 r0 enable slow port ldr r1 0xffffffff ldr r0 0xe0028008 register address IODIR str r1 r0 set port 0 to output ldr r2 0x00100000 select PIO20 ldr r0 0xe0028004 register address IOSET ldr r1 0xe002800C r...

Page 76: ...s Built in fractional baud rate generator with autobauding capabilities Mechanism that enables software and hardware flow control implementation 14 2 Pin description 14 3 Register description UART0 contains registers organized as shown in Table 82 The Divisor Latch Access Bit DLAB is contained in U0LCR 7 and enables access to the divisor latches Fig 17 Illustration of the fast and slow GPIO access...

Page 77: ...a RO n a 0xE000 C000 DLAB 0 U0THR transmit holding register 8 bit write data WO n a 0xE000 C000 DLAB 0 U0DLL divisor latch LSB 8 bit data R W 0x01 0xE000 C000 DLAB 1 U0DLM divisor latch MSB 8 bit data R W 0x00 0xE000 C004 DLAB 1 U0IER interrupt enable register ABTO IntEn ABEO IntEn R W 0x00 0xE000 C004 DLAB 0 RX Line Status Interrupt Enable THRE Interrupt Enable RBR Interrupt Enable U0IIR interrup...

Page 78: ...In order to access the U0THR the Divisor Latch Access Bit DLAB in U0LCR must be logic 0 The U0THR is always write only 14 3 3 UART0 Divisor latch registers U0DLL 0xE000 C000 and U0DLM 0xE000 C004 when DLAB 1 The UART0 Divisor Latch is part of the UART0 Fractional Baud Rate Generator and holds the value used to divide the clock supplied by the fractional prescaler in order to produce the baud rate ...

Page 79: ...e UART0 fractional baud rate generator specific parameters The value of MULVAL and DIVADDVAL must comply with the following conditions 0 MULVAL 15 0 DIVADDVAL 15 Table 85 UART0 Divisor latch LSB register U0DLL address 0xE000 C000 when DLAB 1 bit description Bit Symbol Description Reset value 7 0 DLL UART0 divisor latch LSB register and U0DLM register determine baud rate of UART0 0x01 Table 86 UART...

Page 80: ...e two requests then the fractional divider output is undefined If DIVADDVAL is zero then the fractional divider is disabled and the clock is not divided 14 3 4 1 Baud rate calculation UART can operate with or without using the fractional divider In real life applications it is likely that the desired baud rate can be achieved using several different fractional divider settings The following algori...

Page 81: ...1 067 1 15 1 267 4 15 1 533 8 15 1 769 10 13 1 071 1 14 1 273 3 11 1 538 7 13 1 778 7 9 1 077 1 13 1 286 2 7 1 545 6 11 1 786 11 14 1 083 1 12 1 300 3 10 1 556 5 9 1 800 4 5 1 091 1 11 1 308 4 13 1 571 4 7 1 818 9 11 1 100 1 10 1 333 1 3 1 583 7 12 1 833 5 6 1 111 1 9 1 357 5 14 1 600 3 5 1 846 11 13 aaa 000584 DIVADDVAL table FRest MULVAL table FRest DLM DLest 15 8 DLL DLest 7 0 DIVADDVAL 0 MULVA...

Page 82: ...ART baud rate is 115384 Bd This rate has a relative error of 0 16 from the originally specified value of 115200 Bd 14 3 5 UART0 Interrupt enable register U0IER 0xE000 C004 when DLAB 0 The U0IER is used to enable UART0 interrupt sources 1 125 1 8 1 364 4 11 1 615 8 13 1 857 6 7 1 133 2 15 1 375 3 8 1 625 5 8 1 867 13 15 1 143 1 7 1 385 5 13 1 636 7 11 1 875 7 8 1 154 2 13 1 400 2 5 1 643 9 14 1 889...

Page 83: ...IntEn enables the auto baud time out interrupt 0 0 disables auto baud time out interrupt 1 enables auto baud time out interrupt 31 10 reserved user software must not write logic 1s to reserved bits value read from a reserved bit is not defined n a Table 89 UART0 Interrupt enable register U0IER address 0xE000 C004 when DLAB 0 bit description continued Bit Symbol Value Description Reset value Table ...

Page 84: ...e trigger level The CTI interrupt U0IIR 3 1 110 is a second level interrupt and is set when the UART0 Rx FIFO contains at least one character and no UART0 Rx FIFO activity has occurred in 3 5 to 4 5 character times Any UART0 Rx FIFO activity read or write of UART0 RSR clears the interrupt This interrupt is intended to flush the UART0 RBR after a message is received that is not a multiple of the tr...

Page 85: ...ast THRE 1 event This delay is provided to give the CPU time to write data to U0THR without a THRE interrupt to decode and service If the UART0 THR FIFO has held two or more characters at one time and currently the U0THR is empty a THRE interrupt is set immediately The THRE interrupt is reset when a U0THR write occurs or a read of the U0IIR occurs and the THRE is the highest interrupt U0IIR 3 1 00...

Page 86: ...e must not write logic 1s to reserved bits value read from a reserved bit is not defined n a 7 6 RX Trigger Level determine how many receiver UART0 FIFO characters must be written before an interrupt is activated 0 00 trigger level 0 1 character or 0x01 01 trigger level 1 4 characters or 0x04 10 trigger level 2 8 characters or 0x08 11 trigger level 3 14 characters or 0x0E Table 93 UART0 Line contr...

Page 87: ... error status is inactive 1 parity error status is active 3 Framing Error FE if stop bit of received character is logic 0 a framing error occurs An U0LSR read clears U0LSR 3 Time of framing error detection is dependent on U0FCR0 Upon detection of a framing error Rx attempts to resynchronize to data and assumes bad stop bit is early start bit However it cannot be assumed that next received byte is ...

Page 88: ... status register U0LSR address 0xE000 C014 read only bit description continued Bit Symbol Value Description Reset value Table 95 UART0 Scratch pad register U0SCR address 0xE000 C01C bit description Bit Symbol Description Reset value 7 0 Pad read write byte 0x00 Table 96 Auto baud control register U0ACR 0xE000 C020 bit description Bit Symbol Value Description Reset value 0 Start automatically clear...

Page 89: ...f this bit is set the rate measurement restarts at the next falling edge of pin UART0 Rx The auto baud function can generate two interrupts The U0IIR ABTOInt interrupt is set if the interrupt is enabled U0IER ABToIntEn is set and the auto baud rate measurement counter overflows The U0IIR ABEOInt interrupt is set if the interrupt is enabled U0IER ABEOIntEn is set and the auto baud has completed suc...

Page 90: ...bit is stored in U0RSR 4 During the receipt of the start bit and the character LSB for mode 0 the rate counter continues incrementing with the pre scaled UART0 input clock PCLK 5 If Mode 0 then the rate counter stops on the next falling edge of pin UART0 Rx If Mode 1 then the rate counter stops on the next rising edge of pin UART0 Rx 6 The rate counter is loaded into U0DLM U0DLL and the baud rate ...

Page 91: ... to await access by the CPU or host via the generic host interface The UART0 transmitter block U0TX accepts data written by the CPU or host and buffers the data in the UART0 TX Holding register FIFO U0THR The UART0 TX Shift register U0TSR reads the data stored in the U0THR and assembles the data to transmit via the serial output pin TXD0 a Mode 0 start bit and LSB are used for auto baud b Mode 1 o...

Page 92: ...d by the UART0 TX block The U0BRG clock input source is the APB clock PCLK The main clock is divided down per the divisor specified in registers U0DLL and U0DLM and is a 16 oversample clock NBAUDOUT The interrupt interface contains registers U0IER and U0IIR The interrupt interface receives several one clock wide enables from the U0TX and U0RX blocks Status information from the U0TX and U0RX is sto...

Page 93: ...ual Rev 1 16 December 2011 93 of 268 NXP Semiconductors UM10413 MPT612 User manual Fig 20 UART0 block diagram aaa 000583 APB INTERFACE U0LCR U0RX DDIS U0LSR U0FCR U0BRG U0TX INTERRUPT PA 2 0 PSEL PSTB PWRITE PD 7 0 AR MR PCLK U0INTR U0SCR NTXRDY TXD0 NBAUDOUT RCLK NRXRDY RXD0 U0RBR U0RSR U0DLM U0DLL U0THR U0TSR U0IIR U0IER ...

Page 94: ...ored in U1MSR 4 If enabled U1IER 3 1 state change information is stored in U1MSR 0 and is a source for a priority level 4 interrupt DCD1 input data carrier detect Active LOW signal indicates if external modem has established a communication link with UART1 and data can be exchanged In normal operation of modem interface U1MCR 4 0 complement value of this signal is stored in U1MSR 7 If enabled U1IE...

Page 95: ... LSB 8 bit data R W 0x01 0xE001 0000 DLAB 1 U1DLM Divisor Latch MSB 8 bit data R W 0x00 0xE001 0004 DLAB 1 U1IER Interrupt Enable register ABTO IntEn ABEO Int R W 0x00 0xE001 0004 DLAB 0 CTS Interrupt Enable Modem Status Interrupt Enable RX Line Interrupt Enable THRE Interrupt Enable RBR Interrupt Enable U1IIR Interrupt Identification register ABTO Int ABEO Int RO 0x01 0xE001 0008 FIFO Enable Inte...

Page 96: ...xxxxxxxxxxxxxx xxx UM10413 All information provided in this document is subject to legal disclaimers NXP B V 2011 All rights reserved User manual Rev 1 16 December 2011 96 of 268 NXP Semiconductors UM10413 MPT612 User manual 1 Reset value reflects the data stored in used bits only It does not include the content of reserved bits U1FDR Fractional Divider register reserved 31 8 R W 0x10 0xE001 0028 ...

Page 97: ...ransmit The Divisor Latch Access Bit DLAB in U1LCR must be logic 0 to access the U1THR The U1THR is always write only 15 3 3 UART1 Divisor latch registers 0 and 1 U1DLL 0xE001 0000 and U1DLM 0xE001 0004 when DLAB 1 The UART1 divisor latch is part of the UART1 fractional baud rate generator and holds the value used to divide the clock supplied by the fractional prescaler to produce the baud rate cl...

Page 98: ... MULVAL are UART1 fractional baud rate generator specific parameters The value of MULVAL and DIVADDVAL must comply with the following conditions 0 MULVAL 15 0 DIVADDVAL 15 DIVADDVAL MULVAL Table 102 UART1 Divisor latch LSB register U1DLL address 0xE001 0000 when DLAB 1 bit description Bit Symbol Description Reset value 7 0 DLLSB UART1 divisor latch LSB register and U1DLM register determines baud r...

Page 99: ...T can operate with or without using the fractional divider In real life applications it is likely that the desired baud rate can be achieved using several different fractional divider settings The following algorithm illustrates one way of finding a set of DLM DLL MULVAL and DIVADDVAL values Such set of parameters yields a baud rate with a relative error of less than 1 1 from that desired Fig 21 A...

Page 100: ... 0 DLL 4 DIVADDVAL 5 and MULVAL 8 According to Equation 3 on page 98 the UART s baud rate is 115384 Bd This rate has a relative error of 0 16 from the originally specified value of 115200 Bd 15 3 5 UART1 Interrupt enable register U1IER 0xE001 0004 when DLAB 0 The U1IER is used to enable UART1 interrupt sources Table 105 Fractional divider setting look up table FR DivAddVal MulVal FR DivAddVal MulV...

Page 101: ...his interrupt can be read from U1MSR 3 0 0 0 disables modem interrupt 1 enables modem interrupt 6 4 reserved user software must not write logic 1s to reserved bits value read from a reserved bit is not defined n a 7 CTS Interrupt Enable if auto CTS mode is enabled this bit enables disables the modem status interrupt generation on a CTS1 signal transition If auto CTS mode is disabled a CTS1 transit...

Page 102: ...riority with the CTI interrupt U1IIR 3 1 110 The RDA is activated when the UART1 Rx FIFO reaches the trigger level defined in U1FCR 7 6 and is reset when the UART1 Rx FIFO depth falls below the trigger level When the RDA interrupt goes active the CPU can read a block of data defined by the trigger level Table 107 UART1 Interrupt identification register U1IIR address 0xE001 0008 read only bit descr...

Page 103: ...ditions implement a one character delay minus the stop bit whenever THRE 1 and there have not been at least two characters in the U1THR at one time since the last THRE 1 event This delay is provided to give the CPU time to write data to U1THR without a THRE interrupt to decode and service If the UART1 THR FIFO has held two or more characters at one time and currently the U1THR is empty a THRE inte...

Page 104: ...O Reset 0 no impact on either UART1 FIFO 0 1 writing a logic 1 to U1FCR 2 clears all bytes in UART1 Tx FIFO and resets pointer logic This bit is self clearing 5 3 reserved user software must not write logic 1s to reserved bits value read from a reserved bit is not defined n a 7 6 RX Trigger Level 00 determine how many receiver UART1 FIFO characters must be written before an interrupt is activated ...

Page 105: ...ol register U1MCR address 0xE001 0010 bit description Bit Symbol Value Description Reset value 0 DTR Control source for modem output pin DTR Reads as logic 0 when modem loopback mode is active 0 1 RTS Control source for modem output pin RTS Reads as logic 0 when modem loopback mode is active 0 3 2 reserved user software must not write logic 1s to reserved bits value read from a reserved bit is not...

Page 106: ...RTS is enabled UART1 deasserts the RTS1 output when the receive FIFO contains 8 bytes Table 109 on page 104 The RTS1 output is reasserted when the receive FIFO reaches the previous trigger level 4 bytes Auto CTS The auto CTS function is enabled by setting bit CTSen If auto CTS is enabled the transmitter circuitry in the U1TSR module checks CTS1 input before sending the next data byte When CTS1 is ...

Page 107: ...R 0xE001 0014 read only The U1LSR is a read only register that provides status information on the UART1 Tx and Rx blocks 1 1 1 0 0 no 1 1 1 1 X yes 1 1 1 X 1 yes Table 112 Modem status interrupt generation continued Enable modem statusinterrupt U1IER 3 CTSen U1MCR 7 CTS interrupt enable U1IER 7 Delta CTS U1MSR 0 Delta DCD or trailing edge RI or Delta DSR U1MSR 3 or U1MSR 2 or U1MSR 1 Modem status ...

Page 108: ... is associated with character at top of UART1 RBR FIFO 0 0 framing error status is inactive 1 framing error status is active 4 Break Interrupt BI when RXD1 is held in spacing state all 0s for one full character transmission start data parity stop a break interrupt occurs Once break condition is detected receiver is idle until RXD1 enters marking state all 1s An U1LSR read clears this status bit Ti...

Page 109: ...odem input DSR 1 state change detected on modem input DSR 2 Trailing Edge RI set on LOW to HIGH transition of input RI Cleared on U1MSR read 0 0 no change detected on modem input RI 1 LOW to HIGH transition detected on RI 3 Delta DCD set on state change of input DCD Cleared on an U1MSR read 0 0 no change detected on modem input DCD 1 state change detected on modem input DCD 4 CTS clear to send sta...

Page 110: ...an generate two interrupts The U1IIR ABTOInt interrupt is set if the interrupt is enabled U1IER ABToIntEn is set and the auto baud rate measurement counter overflows The U1IIR ABEOInt interrupt is set if the interrupt is enabled U1IER ABEOIntEn is set and the auto baud has completed successfully The auto baud interrupts have to be cleared by setting the corresponding bits U1ACR ABTOIntClr and ABEO...

Page 111: ...is reset and the UART1 U1RSR is reset The U1RSR baud rate is switched to the highest rate 2 A falling edge on pin UART1 Rx triggers the beginning of the start bit The rate measuring counter starts counting PCLK cycles optionally pre scaled by the fractional baud rate generator 3 During receipt of the start bit 16 pulses are generated on the RSR baud input at the frequency of the fractional baud ra...

Page 112: ... When bit TXEn is logic 0 UART1 transmission stops Table 117 describes how to use bit TXEn to achieve software flow control a Mode 0 start bit and LSB are used for auto baud b Mode 1 only start bit is used for auto baud Fig 24 Auto baud mode 0 and mode 1 waveforms aaa 000637 start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity stop UART1 RX U1ACR start rate counter A 0x41 or a 0x61 16xbaud_rate LS...

Page 113: ...sample clock NBAUDOUT The modem interface contains registers U1MCR and U1MSR This interface is responsible for handshaking between a modem peripheral and the UART1 The interrupt interface contains registers U1IER and U1IIR The interrupt interface receives several one clock wide enables from the U1TX and U1RX blocks Status information from the U1TX and U1RX is stored in the U1LSR Control informatio...

Page 114: ...2C interfaces I2C0 and I2C1 16 1 Features Standard I2C compliant bus interfaces can be configured as Master Slave or Master Slave Fig 25 UART1 block diagram aaa 000588 APB INTERFACE U1LCR U1RX DDIS U1LSR U1FCR U1BRG U1TX INTERRUPT PA 2 0 PSEL PSTB PWRITE PD 7 0 AR MR PCLK U1INTR U1SCR NTXRDY TXD1 NBAUDOUT RCLK NRXRDY RXD1 U1RBR U1RSR U1DLM U1DLL U1THR U1TSR U1IIR U1IER MODEM RTS U1MCR U1MSR DTR DC...

Page 115: ...r transmitter to a slave receiver The first byte transmitted by the master is the slave address Next follows a number of data bytes The slave returns an acknowledge bit after each received byte Data transfer from a slave transmitter to a master receiver The first byte the slave address is transmitted by the master The slave then returns an acknowledge bit Next follows the data bytes transmitted by...

Page 116: ... to slave Before the master transmitter mode can be entered register I2CONSET must be initialized as shown in Table 119 To enable the I2C function I2EN must be set to logic 1 If bit AA is logic 0 the I2C interface will not acknowledge any address when another device is master of the bus so it cannot enter slave mode The STA STO and SI bits must be logic 0 Bit SI is cleared by writing logic 1 to bi...

Page 117: ... mode or 0x68 0x78 or 0xB0 if the slave mode was enabled by setting AA to logic 1 The appropriate actions to be taken for each of these status codes are shown in Table 134 on page 135 to Table 137 on page 139 16 5 2 Master receiver mode In the master receiver mode data is received from a slave transmitter The transfer is initiated in the same way as in the master transmitter mode When the Start co...

Page 118: ... by the data direction bit If the direction bit is logic 0 W it enters slave receiver mode If the direction bit is logic 1 R it enters slave transmitter mode After the address and direction bit have been received bit SI is set and a valid status code can be read from the status register I2STAT Refer to Table 136 on page 137 for the status codes and actions Fig 28 Format of master receiver mode Fig...

Page 119: ...s not interrupted If bus arbitration is lost in the master mode the I2C interface switches to the slave mode immediately and can detect its own slave address in the same serial transfer 16 6 I2C implementation and operation Figure 32 shows how the on chip I2C bus interface is implemented and the following text describes the individual blocks 16 6 1 Input filters and output stages Input signals are...

Page 120: ...l Fig 32 I2C serial interface block diagram aaa 000595 APB BUS STATUS REGISTER CONTROL REGISTER SCL DUTY CYCLE REGISTERS ADDRESS REGISTER COMPARATOR SHIFT REGISTER 8 8 ACK I2ADR I2DAT 8 16 BIT COUNTER ARBITRATION SYNC LOGIC SERIAL CLOCK GENERATOR TIMING CONTROL LOGIC STATUS DECODER status bus I2CONSET I2CONCLR I2SCLH I2SCLL interrupt PCLK INPUT FILTER SCL INPUT FILTER OUTPUT STAGE OUTPUT STAGE SDA...

Page 121: ...sition from master transmitter to slave receiver is made with the correct data in I2DAT 16 6 5 Arbitration and synchronization logic In the master transmitter mode the arbitration logic checks that every transmitted logic 1 actually appears as a logic 1 on the I2C bus If another device on the bus overrules a logic 1 and pulls the SDA line LOW arbitration is lost and the I2C block immediately chang...

Page 122: ...quency and duty cycle is programmable via the I2C Clock Control registers See the description of registers I2CSCLL and I2CSCLH for details The output clock pulses have a duty cycle as programmed unless the bus is synchronizing with other SCL clock sources as described above 16 6 7 Timing and control The timing and control logic generates the timing and control signals for serial byte handling This...

Page 123: ...eserved bits Table 121 I2C register map Name Description Access Reset value 1 I2C0 Address and name I2C1 Address and name I2CONSET I2C control set register If a logic 1 is written to a bit of this register the corresponding bit in I2C control register is set Writing a logic 0 has no effect on the corresponding bit in I2C control register R W 0x00 0xE001 C000 I2C0CONSET 0xE005 C000 I2C1CONSET I2STA...

Page 124: ...master mode it enters master mode checks the bus and generates a Start condition if the bus is free If the bus is not free it waits for a Stop condition which frees the bus and generates a Start condition after a delay of a half clock period of the internal clock generator If the I2C interface is already in master mode and data is transmitted or received it transmits a repeated Start condition STA...

Page 125: ...g the acknowledge clock pulse on the SCL line in the following situations The address in the slave address register is received The general call address is received while the general call bit GC in I2ADR is set A data byte is received while the I2C is in the master receiver mode A data byte is received while the I2C is in the addressed slave receiver mode Bit AA can be cleared by writing logic 1 t...

Page 126: ...se states are entered bit SI is set For a complete list of status codes refer to Table 134 on page 135 to Table 137 on page 139 inclusive 16 7 4 I2C Data register I2DAT I2C0 I2C0DAT 0xE001 C008 and I2C1 I2C1DAT 0xE005 C008 This register contains the data to be transmitted or the data just received The CPU can read and write to this register only while it is not in the process of shifting a byte wh...

Page 127: ...PCLK is the frequency of the peripheral bus APB 5 The values for I2SCLL and I2SCLH must not necessarily be the same Software can set different duty cycles on SCL by setting these two registers For example the I2C bus specification defines the SCL LOW time and HIGH time at different values for a 400 kHz I2C rate The value of the register must ensure that the data rate is in the I2C data rate range ...

Page 128: ...e routines are not critical since the serial transfer is suspended until the serial interrupt flag is cleared by software When a serial interrupt routine is entered the status code in I2STAT is used to branch to the appropriate service routine For each status code the required software action and details of the following serial transfer are given in Table 134 on page 135 to Table 138 on page 141 i...

Page 129: ...et again and a number of status codes in I2STAT are possible There are 0x18 0x20 or 0x38 for the master mode and also 0x68 0x78 or 0xB0 if the slave mode was enabled AA logic 1 The appropriate action to take for each of these status codes is detailed in Table 134 on page 135 After a repeated Start condition state 0x10 The I2C block can switch to the master receiver mode by loading I2DAT with SLA R...

Page 130: ...er its own slave address and bit W are received the serial interrupt flag SI is set and a valid status code can be read from I2STAT This status code is used to vector to a state service routine The appropriate action to be taken for each of these status codes is detailed in Table 136 on page 137 The slave receiver mode can also be entered if arbitration is lost while the I2C block is in the master...

Page 131: ...ter continues Other Master continues 20H 08H 18H 28H 30H 10H 68H 78H B0H 38H 38H From Master to Slave From Slave to Master Any number of data bytes and their associated Acknowledge bits n This number contained in I2STA corresponds to a defined state of the I2C bus A P P S P Successful transmission to a Slave Receiver Next transfer started with a Repeated Start condition Not Acknowledge received af...

Page 132: ...er continues A Other Master continues Other Master continues 48H 08H 40H 58H 10H 68H 78H B0H 38H 38H From Master to Slave From Slave to Master Any number of data bytes and their associated Acknowledge bits n This number contained in I2STA corresponds to a defined state of the I2C bus P S P Successful transmission to a Slave Transmitter Next transfer started with a Repeated Start condition Not Ackn...

Page 133: ...ter Any number of data bytes and their associated Acknowledge bits n This number contained in I2STA corresponds to a defined state of the I2C bus S Reception of the own Slave Address and one or more Data bytes are all acknowledged Last data byte received is Not Acknowledged Arbitration lost as Master and addressed as Slave Reception of the General Call address and one or more Data bytes Last data ...

Page 134: ...t while the I2C block is in the master mode see state 0xB0 If bit AA is reset during a transfer the I2C block transmits the last byte of the transfer and enters state 0xC0 or 0xC8 The I2C block is switched to the not addressed slave mode and ignores the master receiver if it continues the transfer Thus the master receiver receives all logic 1s as serial data While AA is reset the I2C block does no...

Page 135: ...W transmitted NOT ACK received load data byte or 0 0 0 X data byte transmitted ACK bit received no I2DAT action or 1 0 0 X repeated start transmitted no I2DAT action or 0 1 0 X stop condition transmitted STO flag reset no I2DAT action 1 1 0 X stop condition followed by a start condition transmitted STO flag reset 0x28 data byte in I2DAT transmitted ACK received load data byte or 0 0 0 X data byte ...

Page 136: ...e mode no I2DAT action 1 0 0 X a start condition is transmitted when the bus is free 0x40 SLA R transmitted ACK received no I2DAT action or 0 0 0 0 data byte received NOT ACK bit returned no I2DAT action 0 0 0 1 data byte received ACK bit returned 0x48 SLA R transmitted NOT ACK received no I2DAT action or 1 0 0 X repeated start condition transmitted no I2DAT action or 0 1 0 X stop condition transm...

Page 137: ...ed ACK returned no I2DAT action or X 0 0 0 data byte received and NOT ACK returned no I2DAT action X 0 0 1 data byte received and ACK returned 0x80 previously addressed with own SLV address data received ACK returned read data byte or X 0 0 0 data byte received and NOT ACK returned read data byte X 0 0 1 data byte received and ACK returned 0x88 previously addressed with own SLA data byte received ...

Page 138: ...ll address recognized if I2ADR 0 logic 1 A start condition is transmitted when the bus is free 0xA0 a stop condition or repeated start condition received while still addressed as SLV REC or SLV TRX no STDAT action or 0 0 0 0 switched to not addressed SLV mode no recognition of own SLA or general call address no STDAT action or 0 0 0 1 switched to not addressed SLV mode own SLA recognized general c...

Page 139: ...it received 0xC0 data byte in I2DAT transmitted NOT ACK received no I2DAT action 0 0 0 0 switched to not addressed SLV mode no recognition of own SLA or general call address no I2DAT action 0 0 0 1 switched to not addressed SLV mode own SLA recognized general call address recognized if I2ADR 0 logic 1 no I2DAT action 1 0 0 0 switched to not addressed SLV mode no recognition of own SLA or general c...

Page 140: ...bus error has occurred during an I2C serial transfer A bus error is caused when a Start or Stop condition occurs at an illegal position in the format frame Examples of such illegal positions are during the serial transfer of an address byte a data byte or an acknowledge bit A bus error can also be caused when external interference disturbs the internal I2C block signals When a bus error occurs SI ...

Page 141: ... 0x78 and 0xB0 see Figure 35 on page 131 and Figure 36 on page 132 If the STA flag in I2CON is set by the routines which service these states then if the bus is free again a Start condition state 0x08 is transmitted without intervention by the CPU and a retry of the total serial transfer can commence 16 8 11 Forced access to the I2C bus In some applications it can be possible for an uncontrolled s...

Page 142: ...ition after every two additional clock pulses on the SCL line When the SDA line is eventually released a normal Start condition is transmitted state 0x08 is entered and the serial transfer continues If a forced bus access occurs or a repeated Start condition is transmitted while SDA is obstructed pulled LOW the I2C hardware performs the same action as described above In each case state 0x08 is ent...

Page 143: ...s used for transmission and reception The initialization routine performs the following functions I2ADR is loaded with the part s own slave address and the general call bit GC The I2C interrupt enable and interrupt priority bits are set Slave mode is enabled by simultaneously setting the I2EN and AA bits in I2CON and the serial clock frequency for master modes is defined by loading CR0 and CR1 in ...

Page 144: ...se states can never occur In an application it may be desirable to implement some kind of time out during I2C operations in order to trap an inoperative bus or a lost service routine 16 9 Software example 16 9 1 Initialization routine Example to initialize I2C interface as a slave and or master 1 Load I2ADR with own slave address enable general call recognition if needed 2 Enable I2C interrupt 3 W...

Page 145: ...NCLR to clear the SI flag 3 Exit 16 9 5 2 Master states State 08 and state 10 are for both master transmit and master receive modes Bit R W decides whether the next state is within master transmit mode or master receive mode 16 9 5 3 State 0x08 A Start condition is transmitted The slave address bit R W is transmitted an ACK bit is received 1 Write slave address with bit R W to I2DAT 2 Write 0x04 t...

Page 146: ...8 to I2CONCLR to clear the SI flag 3 Exit 16 9 6 3 State 0x28 Data is transmitted ACK is received If the transmitted data was the last data byte then transmit a Stop condition otherwise transmit the next data byte 1 Decrement the master data counter skip to step 5 if not the last data byte 2 Write 0x14 to I2CONSET to set the STO and AA bits 3 Write 0x08 to I2CONCLR to clear the SI flag 4 Exit 5 Lo...

Page 147: ...ite 0x14 to I2CONSET to set the STO and AA bits 2 Write 0x08 to I2CONCLR to clear the SI flag 3 Exit 16 9 7 3 State 0x50 Data is received ACK is returned Data is read from I2DAT Additional data is received If this is the last data byte then NOT ACK is returned otherwise ACK is returned 1 Read data byte from I2DAT into master receive buffer 2 Decrement the master data counter skip to step 5 if not ...

Page 148: ...0x24 to I2CONSET to set the STA and AA bits 2 Write 0x08 to I2CONCLR to clear the SI flag 3 Set up slave receive mode data buffer 4 Initialize slave data counter 5 Exit 16 9 8 3 State 0x70 General call is received ACK is returned Data is received and ACK returned 1 Write 0x04 to I2CONSET to set bit AA 2 Write 0x08 to I2CONCLR to clear the SI flag 3 Set up slave receive mode data buffer 4 Initializ...

Page 149: ...he SI flag 3 Exit 16 9 8 7 State 0x90 Previously addressed with general call Data is received ACK is returned Received data is saved Only the first data byte is received with ACK Additional data is received with NOT ACK 1 Read data byte from I2DAT into the slave receive buffer 2 Write 0x0C to I2CONCLR to clear the SI flag and bit AA 3 Exit 16 9 8 8 State 0x98 Previously addressed with general call...

Page 150: ...ve transmit buffer with first data byte 2 Write 0x24 to I2CONSET to set the STA and AA bits 3 Write 0x08 to I2CONCLR to clear the SI flag 4 Set up slave transmit mode data buffer 5 Increment slave transmit buffer pointer 6 Exit 16 9 9 3 State 0xB8 Data is transmitted ACK is received Data is transmitted ACK bit is received 1 Load I2DAT from slave transmit buffer with data byte 2 Write 0x04 to I2CON...

Page 151: ...ransfer During a data transfer the master always sends 8 to 16 bits of data to the slave and the slave always sends a byte of data to the master 17 2 2 SPI data transfers Figure 42 is a timing diagram that illustrates the four different data transfer formats that are available with the SPI This timing diagram illustrates a single 8 bit data transfer The timing diagram is divided into three horizon...

Page 152: ... master can activate the clock and begin the transfer The transfer ends when the last clock cycle of the transfer is complete Fig 42 SPI data transfer format CPHA 0 and CPHA 1 aaa 000605 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 B...

Page 153: ...he SPI data register for the transmit case There is no buffer between the data register and the internal shift register A write to the data register goes directly into the internal shift register Therefore data must only be written to this register when a transmit is not currently in progress Read data is buffered When a transfer is complete the receive data is transferred to a single byte data bu...

Page 154: ...s no write buffer between the SPI block bus interface and the internal shift register As a result data must not be written to the SPI data register when a SPI data transfer is currently in progress The time frame where data cannot be written to the SPI data register is from when the transfer starts until after the status register been read when the SPIF status is active If the SPI data register is...

Page 155: ...hat was received is thrown away There are no other indications of this exception This signal is not directly driven by the master It can be driven by a simple general purpose I O under software control On pin MPT612 SSEL0 can be used for a different function when the SPI0 interface is only used in Master mode For example the pin hosting the SSEL0 function can be configured as an output digital GPI...

Page 156: ...e A transfer starts with the first clock edge and ends with the last sampling edge when SSEL signal is active 4 CPOL clock polarity control 0 0 SCK is active HIGH 1 SCK is active LOW 5 MSTR Master mode select 0 0 SPI operates in Slave mode 1 SPI operates in Master mode 6 LSBF LSB first Controls which direction each byte is shifted when transferred 0 0 SPI data is transferred MSB bit 7 first 1 SPI ...

Page 157: ...software must not write logic 1s to reserved bits value read from a reserved bit is not defined n a 3 ABRT slave abort If logic 1 indicates that a slave abort has occurred Cleared by reading this register 0 4 MODF Mode fault If logic 1 indicates that a mode fault error has occurred Cleared by reading this register then writing the SPI0 control register 0 5 ROVR read overrun If logic 1 indicates th...

Page 158: ...SPINT address 0xE002 001C bit description Bit Symbol Description Reset value 0 SPI Interrupt Flag SPI interrupt flag Set by SPI interface to generate an interrupt Cleared by writing a logic 1 to this bit Remark set once when SPIE 1 and at least one SPIF or bit WCOL is logic 1 However only when SPI interrupt bit is set and SPI0 interrupt is enabled in VIC can SPI based interrupt be processed by int...

Page 159: ...nly a single master and a single slave can communicate on the bus during a given data transfer Data transfers are in principle full duplex with frames of 4 to 16 bit data flowing from the master to the slave and from the slave to the master In practice often only one of these data flows carries meaningful data Table 147 SSP pin descriptions Pin Name Type Interface pin name function Pin description...

Page 160: ...me Sync or Slave Select signal from the master can be connected directly to the slave s corresponding input If there is more than one slave on the bus further qualification of their Frame Select Slave Select inputs will typically be necessary to prevent more than one slave from responding to a transfer MISO1 I O MISO DR M DX S SI M SO S Master In Slave Out The MISO signal transfers serial data fro...

Page 161: ...lock each data bit into their serial shifter on the falling edge of each CLK The received data is transferred from the serial shifter to the receive FIFO on the first rising edge of CLK after the LSB has been latched 18 3 2 SPI frame format The SPI interface is a four wire interface where the SSEL signal behaves as a slave select The main feature of the SPI format is that the inactive state and ph...

Page 162: ... SPI format with CPOL 0 CPHA 0 are shown in Figure 45 In this configuration during idle periods The CLK signal is forced LOW SSEL is forced HIGH The transmit MOSI MISO pad is in high impedance If the SSP is enabled and there is valid data within the transmit FIFO the start of transmission is signified by the SSEL master signal being driven LOW This enables slave data onto the MISO input line of th...

Page 163: ...ptured 18 3 5 SPI format with CPOL 0 CPHA 1 The transfer signal sequence for SPI format with CPOL 0 CPHA 1 is shown in Figure 46 which covers both single and continuous transfers In this configuration during idle periods CLK signal is forced LOW SSEL is forced HIGH The transmit MOSI MISO pad is in high impedance If the SSP is enabled and there is valid data within the transmit FIFO the start of tr...

Page 164: ...e data to be immediately transferred onto the MISO line of the master Master s pin MOSI is enabled One half period later valid master data is transferred to the MOSI line Now that both the master and slave data have been set the SCK master clock pin goes LOW after one further half SCK period This means that data is captured on the falling edges and is propagated on the rising edges of the SCK sign...

Page 165: ...abled and there is valid data within the transmit FIFO the start of transmission is signified by the SSEL master signal being driven LOW Master s MOSI is enabled After a further one half SCK period both master and slave data are enabled onto their respective transmission lines At the same time the SCK is enabled with a falling edge transition Data is then captured on the rising edges and propagate...

Page 166: ... CS remains LOW for the duration of the frame transmission Pin SI remains tri stated during this transmission The off chip serial slave device latches each control bit into its serial shifter on the rising edge of each SK After the last bit is latched by the slave device the control byte is decoded during a one clock wait state and the slave responds by transmitting data back to the SSP Each bit i...

Page 167: ... a setup of at least twice the period of SK on which the SSP operates With respect to the SK rising edge previous to this edge CS must have a hold of at least one SK period 18 4 Register description The SSP contains 9 registers as shown in Table 148 All registers are byte halfword and word accessible Fig 50 Microwire frame format continuous transfers SK CS SO MSB LSB LSB SI LSB 0 MSB 4 to 16 bits ...

Page 168: ...SPICR interrupt clear register WO NA 0xE006 8020 Table 148 SSP register map continued Name Description Access Reset value 1 Address Table 149 SSP Control register 0 SSPCR0 address 0xE006 8000 bit description Bit Symbol Value Description Reset value 3 0 DSS data size select Controls number of bits transferred in each frame Values 0000 0010 are not supported and must not be used 0000 0011 4 bit tran...

Page 169: ...CLK CPSDVSR SCR 1 0x00 Table 149 SSP Control register 0 SSPCR0 address 0xE006 8000 bit description continued Bit Symbol Value Description Reset value Table 150 SSP Control register 1 SSPCR1 address 0xE006 8004 bit description Bit Symbol Value Description Reset value 0 LBM Loop back Mode 0 0 during normal operation 1 serial input is taken from serial output MOSI or MISO rather than serial input pin...

Page 170: ...sent when all previous data has been sent and received If data length is less than 16 bits software must right justify data written to this register Read software can read data from this register whenever bit RNE in the status register is logic 1 indicating that Rx FIFO is not empty When software reads this register SSP controller returns data from least recent frame in Rx FIFO If data length is l...

Page 171: ...tware must set this bit to enable interrupt when a receive overrun occurs that is when Rx FIFO is full and another frame is received The ARM specification implies that preceding frame data is overwritten by new frame data when this occurs 0 1 RTIM receive time out interrupt Software must set this bit to enable interrupt when a receive time out condition occurs A receive time out occurs when Rx FIF...

Page 172: ...divider is included in each converter to scale this clock to the 4 5 MHz maximum clock needed by the successive approximation process A fully accurate conversion requires 11 of these clocks Table 156 SSP Masked interrupt status register SSPMIS address 0xE006 801C bit description Bit Symbol Description Reset value 0 RORMIS logic 1 if another frame was received while Rx FIFO was full and this interr...

Page 173: ...nd ground Must nominally be the same voltages as VDD and GND but must be isolated to minimize noise and error VDD ADC also provides the ADC voltage reference level VRef Remark If ADC is not used VDD ADC must still be tied to VDD IO and GNDADC must be grounded These pins must not be left floating Table 159 ADC registers Generic name Description Access Reset value 1 AD0 Address and name ADCR A D con...

Page 174: ...g source a slower clock may be desirable 0 16 BURST 1 ADC repeats conversions at the rate selected by CLKS field scanning if necessary through the pins selected by 1s in the SEL field The first conversion after the start corresponds to the least significant 1 in the SEL field then higher numbered 1 bits pins if applicable Repeated conversions can be terminated by clearing this bit but the conversi...

Page 175: ... bits value read from a reserved bit is not defined n a Table 160 A D Control register AD0CR address 0xE003 4000 bit description continued Bit Symbol Value Description Reset value Table 161 A D Global data register AD0GDR address 0xE003 4004 bit description Bit Symbol Description Reset value 5 0 reserved user software must not write logic 1s to reserved bits value read from a reserved bit is not d...

Page 176: ...12 OVERRUN4 mirrors the OVERRRUN status flag from result register for A D channel 4 0 13 OVERRUN5 mirrors the OVERRRUN status flag from result register for A D channel 5 0 14 OVERRUN6 mirrors the OVERRRUN status flag from result register for A D channel 6 0 15 OVERRUN7 mirrors the OVERRRUN status flag from result register for A D channel 7 0 16 ADINT A D interrupt flag It is logic 1 when any of th...

Page 177: ...n on page 62 For the pin hosting an ADC input it is not possible to have a digital function selected and also get valid ADC readings An inside circuit disconnects ADC hardware from the associated pin whenever a digital function is selected on that pin 8 ADGINTEN 0 only the individual ADC channels enabled by ADINTEN7 0 generates interrupts 1 1 only the global DONE flag in ADDR is enabled to generat...

Page 178: ...hange allowed is dependent upon the PWM peripheral clock frequency and the chosen switching frequency The highest resolution is defined as 1 2n where n defines the bit resolution If the highest resolution chosen was say 8 then the change in duty cycle resolution would be 1 28 1 256 0 39 duty cycle This resolution allows the system to correctly track the Maximum Power point of the PV The switching ...

Page 179: ...ities Set LOW on match Set HIGH on match Toggle on match Do nothing on match Up to four match registers can be configured as PWM allowing to use up to three match outputs as single edge controlled PWM outputs 21 2 Applications Interval timer for counting internal events Pulse width demodulator via capture inputs Free running timer Pulse width modulator via match outputs 21 3 Description The timer ...

Page 180: ... HIGH or do nothing The external match register EMR and the PWM control register PWMCON control the functionality of this output all Match signals and their selection pins are listed below MAT1 0 PIO12 MAT1 1 PIO13 MAT1 2 PIO19 MAT1 3 PIO20 Table 166 Timer counter1 register map Generic name Description Access Reset value 1 Timer counter1 address and name IR interrupt register IR can be written to ...

Page 181: ... CR0 capture register 0 CR0 is loaded with value of TC when there is an event on CAPn 0 CAP1 0 respectively input RO 0 0xE000 802C T1CR0 CR1 capture register 1 see CR0 description RO 0 0xE000 8030 T1CR1 CR2 capture register 2 see CR0 description RO 0 0xE000 8034 T1CR2 CR3 capture register 3 see CR0 description RO 0 0xE000 8038 T1CR3 EMR external match register EMR controls match function and exter...

Page 182: ...CLK clock are used to identify only one edge on the CAP selected input the frequency of the CAP input cannot exceed one half of the PCLK clock Consequently duration of the HIGH LOW levels on the same CAP input in this case cannot be shorter than 1 PCLK Table 168 Timer control register TCR TIMER1 T1TCR address 0xE000 8004 bit description Bit Symbol Description Reset value 0 Counter Enable if logic ...

Page 183: ... the next PCLK This causes the TC to increment on every PCLK when PR 0 every 2 PCLKs when PR 1 and so on 21 5 7 Match registers MR0 MR3 The match register values are continuously compared to the timer counter value When the two values are equal actions can be triggered automatically The action possibilities are to generate an interrupt reset the timer counter or stop the timer Actions are controll...

Page 184: ... bit description Bit Symbol Value Description Reset value 0 MR0I 1 interrupt on MR0 an interrupt is generated when MR0 matches the value in TC 0 0 interrupt is disabled 1 MR0R 1 reset on MR0 TC is reset if MR0 matches it 0 0 feature disabled 2 MR0S 1 stop on MR0 TC and PC are stopped and TCR 0 is set to 0 if MR0 matches TC 0 0 feature disabled 3 MR1I 1 interrupt on MR1 an interrupt is generated wh...

Page 185: ...ce of 0s then 1s on CAPn 1 causes CR1 to be loaded with the contents of TC 0 0 feature is disabled 4 CAP1FE 1 capture on CAPn 1 falling edge a sequence of 1s then 0s on CAPn 1 causes CR1 to be loaded with the contents of TC 0 0 feature is disabled 5 CAP1I 1 interrupt on CAPn 1 event a CR1 load due to a CAPn 1 event generates an interrupt 0 0 feature is disabled 6 CAP2RE 1 capture on CAPn 2 rising ...

Page 186: ...ected to its pin When a match occurs between TC and MR1 this output of the timer can either toggle go LOW go HIGH or do nothing Bits EMR 7 6 control the functionality of this output 0 2 EM2 external match 2 Reflects the state of output MAT1 2 whether this output is connected to its pin When a match occurs between TC and MR2 this output of the timer can either toggle go LOW go HIGH or do nothing Bi...

Page 187: ...de positive pulse with a period determined by the PWM cycle length that is the timer reload value If a match register is set to zero then the PWM output goes HIGH the first time the timer returns to zero and stays HIGH continuously Remark If the match outputs are selected to perform as PWM outputs the timer reset MRnR and timer stop MRnS bits in the match control register MCR must be set to zero e...

Page 188: ...op and generate an interrupt on match The prescaler is again set to 2 and the match register set to 6 In the next clock after the timer reaches the match value the timer enable bit in TCR is cleared and the interrupt indicating that a match occurred is generated Fig 52 Sample PWM waveforms with a PWM cycle length of 100 selected by MR3 and MAT3 0 enabled as PWM outputs by register PWCON aaa 000615...

Page 189: ...tures A 16 bit timer counter with a programmable 16 bit prescaler Fig 55 Timer1 block diagram aaa 000618 INTERRUPT REGISTER CONTROL EXTERNAL MATCH REGISTER MATCH CONTROL REGISTER MATCH REGISTER 3 MATCH REGISTER 2 MATCH REGISTER 1 MATCH REGISTER 0 CAPTURE CONTROL REGISTER TIMER CONTROL REGISTER PRESCALE REGISTER LOAD 3 0 RESET ON MATCH STOP ON MATCH CAP 3 0 MAT 3 0 INTERRUPT CAPTURE REGISTER 0 TIME...

Page 190: ...tputs to be used 22 2 Applications Interval timer for counting internal events Free running timer Pulse width modulator via match outputs 22 3 Description The timer counter is designed to count cycles of the peripheral clock PCLK or an externally supplied clock and it can optionally generate interrupts or perform other actions at specified timer values based on four match registers Due to the limi...

Page 191: ...ter can be disabled or reset by TCR R W 0 0xE007 4004 T3TCR TC timer counter 16 bit TC is incremented every PR 1 cycles of PCLK TC is controlled by TCR R W 0 0xE007 4008 T3TC PR prescale register Prescale counter below is equal to this value Next clock increments TC and clears PC R W 0 0xE007 400C T3PR PC prescale counter 16 bit PC is a counter which is incremented to the value stored in PR When t...

Page 192: ...oes not cause an interrupt but a match register can be used to detect an overflow if needed Table 177 Interrupt register IR TIMER3 T3IR address 0xE007 4000 bit description Bit Symbol Description Reset value 0 MR0 Interrupt interrupt flag for match channel 0 0 1 MR1 Interrupt interrupt flag for match channel 1 0 2 MR2 Interrupt interrupt flag for match channel 2 0 3 MR3 Interrupt interrupt flag for...

Page 193: ...e timer Actions are controlled by the settings in the MCR 22 5 8 Match control register MCR TIMER3 T3MCR 0xE007 4014 The match control register is used to control what operations are performed when one of the match registers matches the timer counter The function of each of the bits is shown in Table 180 Table 180 Match control register MCR TIMER3 T3MCR address 0xE007 4014 bit description Bit Symb...

Page 194: ...put can either toggle go LOW go HIGH or do nothing Bits EMR 5 4 control the functionality of this output 0 1 EM1 external match 1 Reflects the state of output MAT3 1 whether this output is connected to its pin If a match occurs between TC and MR1 this timer output can either toggle go LOW go HIGH or do nothing Bits EMR 7 6 control the functionality of this output 0 2 EM2 external match 2 Reflects ...

Page 195: ...tput goes HIGH when its match value is reached If no match occurs that is the match value is greater than the PWM cycle length the PWM output remains continuously LOW If a match value larger than the PWM cycle length is written to the match register and the PWM signal is HIGH already then the PWM signal is cleared on the next start of the next PWM cycle Table 182 External match control EMR 11 10 E...

Page 196: ...rresponding match register 22 6 Example timer operation Figure 53 on page 188 shows a timer configured to reset the count and generate an interrupt on match The prescaler is set to 2 and the match register set to 6 At the end of the timer cycle where the match occurs the timer count is reset which gives a full length cycle to the match value The interrupt indicating that a match occurred is genera...

Page 197: ... December 2011 197 of 268 NXP Semiconductors UM10413 MPT612 User manual 22 7 Architecture The block diagram for timer counter3 is shown in Figure 59 Fig 58 A timer cycle in which PR 2 MRx 6 and both interrupt and stop on match are enabled aaa 000621 PCLK prescale counter 2 4 5 6 0 1 2 0 timer counter TCR 0 counter enable interrupt 1 0 ...

Page 198: ... Debug mode 1 The capture registers are not available on TIMER3 Fig 59 Timer3 block diagram aaa 000622 INTERRUPT REGISTER CONTROL EXTERNAL MATCH REGISTER MATCH CONTROL REGISTER MATCH REGISTER 3 MATCH REGISTER 2 MATCH REGISTER 1 MATCH REGISTER 0 CAPTURE CONTROL REGISTER TIMER CONTROL REGISTER PRESCALE REGISTER LOAD 3 0 RESET ON MATCH STOP ON MATCH CAP2 2 0 MATn 3 0 INTERRUPT CAPTURE REGISTER 0 1 TI...

Page 199: ...reset and boot up procedures see Section 10 10 Reset on page 52 23 3 Description The watchdog consists of a divide by 4 fixed pre scaler and a 32 bit counter The clock is fed to the timer via a pre scaler The timer decrements when clocked The minimum value from which the counter decrements is 0xFF Setting a value lower than 0xFF causes 0xFF to be loaded in the counter Hence the minimum watchdog in...

Page 200: ...atchdog mode register Contains basic mode and status of watchdog timer R W 0 0xE000 0000 WDTC watchdog timer constant register Determines time out value R W 0xFF 0xE000 0004 WDFEED watchdog feed sequence register Writing 0xAA followed by 0x55 to this register reloads watchdog timer to its preset value WO NA 0xE000 0008 WDTV watchdog timer value register Reads out current value of watchdog timer RO...

Page 201: ... the watchdog is enabled The interrupt reset is generated during the second PCLK following an incorrect access to a watchdog timer register during a feed sequence Remark Interrupts must be disabled during the feed sequence If an interrupt occurs during the feed sequence an abort condition occurs 23 4 4 WatchDog timer value register WDTV 0xE000 000C Register WDTV is used to read the current value o...

Page 202: ... MPT612 Deep power down mode is implemented in addition to Idle and Power down modes see Section 24 6 14 on page 210 1 Counter is enabled only when bit WDEN is set and a valid feed sequence is done 2 WDEN and WDRESET are sticky bits Once set they cannot be cleared until the watchdog timer underflows or an external reset occurs Fig 60 Watchdog timer block diagram WDTC 32 BIT DOWN COUNTER CURRENT WD...

Page 203: ...4 3 Description The Real Time Clock RTC is a set of counters for measuring time when system power is on and optionally when it is off It uses little power in Power down mode On the MPT612 the RTC can be clocked by a separate 32 768 kHz oscillator or by a programmable prescale divider based on the APB clock The RTC is powered by its own power supply pin VDD RTC which must be connected to a battery ...

Page 204: ...n this pin supplies the power to RTC Remark VDD RTC must always be connected to either pin VDDC or an independent power supply external battery If VDDC is present RTC battery is disconnected and RTC is powered from VDDC to conserve battery power see Section 24 7 1 Table 191 Real time clock RTC register map Name Size Description Access Reset value 1 Address ILR 2 interrupt location register R W NC ...

Page 205: ... the value in their corresponding time counter then an interrupt is generated If the RTC is operating from its own oscillator on the RTCX1 2 pins the RTC interrupt can bring the MPT612 out of Power down or Deep power down mode When the RTC interrupt is enabled for wake up and its selected event occurs the oscillator wake up cycle associated with the X1 2 pins is started For details on the RTC base...

Page 206: ...rols the function of clock divider R W 0xE002 4008 CIIR 8 counter increment interrupt Selects which counters generate an interrupt when they are incremented R W 0xE002 400C AMR 8 alarm mask register Controls which alarm registers are masked R W 0xE002 4010 CTIME0 32 consolidated time register 0 RO 0xE002 4014 CTIME1 32 consolidated time register 1 RO 0xE002 4018 CTIME2 32 consolidated time registe...

Page 207: ...n Bit Symbol Description Reset value 0 CLKEN clock enable If logic 1 time counters are enabled When logic 0 they are disabled so that they can be initialized n a 1 CTCRST CTC reset If logic 1 the elements in the Clock Tick Counter are reset The elements remain reset until CCR 1 is changed to logic 0 n a 3 2 reserved user software must not write logic 1s to reserved bits value read from a reserved ...

Page 208: ... counter addresses must be used to write new values to the time counters 24 6 9 Consolidated time register 0 CTIME0 0xE002 4014 The consolidated time register 0 contains the low order time values seconds minutes hours and day of week Table 197 Alarm mask register AMR address 0xE002 4010 bit description Bit Symbol Description Reset value 0 AMRSEC if logic 1 the second value is not compared for the ...

Page 209: ...lue Table 199 Consolidated time register 1 CTIME1 address 0xE002 4018 bit description Bit Symbol Description Reset value 4 0 Day of Month day of month value in the range 1 to 28 29 30 or 31 depending on the month and whether it is a leap year n a 7 5 reserved user software must not write logic 1s to reserved bits value read from a reserved bit is not defined n a 11 8 Month month value in the range...

Page 210: ...fully powered up and can be used to store information while the rest of the chip is powered down The registers are available in newer versions of the MPT612 only see Section 24 1 Introduction on page 202 Day of Year 9 Hour 1 365 or 366 for leap year Month 4 Day of Month 1 12 Year 12 Month or day of Year 0 4095 Table 202 Time counter registers Name Size Description Access Address SEC 6 seconds valu...

Page 211: ...on page 39 24 6 16 Alarm register group The alarm registers are shown in Table 205 The values in these registers are compared with the time counters If all the unmasked See Section 24 6 7 on page 208 alarm registers match their corresponding time counters then an interrupt is generated The interrupt is cleared when a logic 1 is written to bit one of the interrupt location register ILR 1 Table 204 ...

Page 212: ...C clock source is switched between the PCLK and the RTCX pins Once the 32 kHz signal from RTCX1 2 pins is selected as a clock source the RTC can operate completely without the presence of the APB clock PCLK Therefore power sensitive applications that is battery powered application utilizing the RTC reduce the power consumption by using the signal from RTCX1 2 pins and writing a logic 0 to bit PCRT...

Page 213: ... 32 768 kHz reference clock from any peripheral clock frequency greater than or equal to 65 536 kHz 2 32 768 kHz This permits the RTC to run always at the proper rate regardless of the peripheral clock rate Basically the prescaler divides the peripheral clock PCLK by a value which contains both an integer portion and a fractional portion The result is not a continuous output at a constant frequenc...

Page 214: ...r of cycles per second can be turned into a 32 kHz reference clock for the RTC The only caveat is that if PREFRAC does not contain a zero then not all of the 32 768 per second clocks are of the same length Some of the clocks are one PCLK longer than others While the longer pulses are distributed as evenly as possible among the remaining pulses this jitter could possibly be of concern in an applica...

Page 215: ...lf of the cycles counted by the 13 bit counter need to be longer If there is a logic 1 in the LSB of the fraction counter the logic causes every alternate count whenever the LSB of the fraction counter 1 to extend by one PCLK evenly distributing the pulse widths Similarly a logic 1 in PREFRAC bit 13 representing the fraction 1 4 causes every fourth cycle whenever the two LSBs of the fraction count...

Page 216: ... slightly different frequency depending on the quality of the crystal compared to the specified one Therefore for an accurate time reference it is advised to use the load capacitors as specified in Table 210 that belong to a specific CL The value of external capacitances CX1 and CX2 specified in this table are calculated from the internal parasitic capacitances and the CL Parasitics from PCB and p...

Page 217: ...ovides the means to accomplish programming of the flash memory This could be initial programming of a blank device erasure and reprogramming of a previously programmed device or programming of the flash memory by the application program in a running system 25 3 Features In System Programming In System Programming ISP is the programming or reprogramming of the on chip flash memory using the bootloa...

Page 218: ...efined state Otherwise unintended entry into ISP mode can occur 25 5 1 Memory map after any reset The boot block is 8 kB in size and resides in the top of the on chip memory space starting from 0x7FFF E000 Both the ISP and IAP software use parts of the on chip RAM The RAM usage is described later The interrupt vectors residing in the boot block of the on chip flash memory also become active after ...

Page 219: ...eater than or equal to 10 MHz The on chip PLL is not used by the boot code Once the crystal frequency is received the part is initialized and the ISP command handler is invoked For safety reasons an Unlock command is required before executing the commands resulting in flash erase write operations and the Go command The rest of the commands can be executed without the Unlock command The Unlock comm...

Page 220: ... chip flash memory is not accessible during erase write operations When the user application code starts executing the interrupt vectors from the user flash area are active The user must either disable interrupts or ensure that user interrupt vectors are active in RAM and that the interrupt handlers reside in RAM before making a flash erase write IAP call The IAP code does not use or disable inter...

Page 221: ...0413 MPT612 User manual 25 5 14 Boot process flowchart 1 Code Read Protection Fig 65 Boot process flowchart CRP2 level only aaa 000628 RESET CRP 1 ENABLED WATCHDOG FLAG SET Enter ISP MODE PIO14 LOW USER CODE VALID AUTO BAUD SUCCESSFUL INITIALIZE ENABLE DEBUG RUN AUTO BAUD RECEIVE CRYSTAL FREQUENCY RUN ISP COMMAND HANDLER no no no no no yes yes yes yes yes EXECUTE INTERNAL USER CODE ...

Page 222: ...the boot block The boot block is present at addresses 0x7FFF E000 to 0x7FFF FFFF in all devices ISP and IAP commands do not allow write erase go operation on the boot block The entire 32 kB of flash memory on the MPT612 is available for the user s application and nxLibMpt firmware Fig 66 Boot process flow chart CRP1 2 3 levels implemented see Section 25 1 on page 217 019aac141 CRP1 2 3 ENABLED WAT...

Page 223: ...e evaluated If the ECC mechanism detects a single error in the fetched data a correction is applied before data are provided to the CPU If a write request into the user s flash is made a write of user specified content is accompanied by a matching ECC value calculated and stored in the ECC memory When a sector of flash memory is erased the corresponding ECC bytes are also erased Once an ECC byte i...

Page 224: ...ntegrity of the flash CRP2 0x87654321 access to chip via the JTAG pins is disabled The following ISP commands are disabled read memory write to RAM go copy RAM to flash compare when CRP2 is enabled the ISP erase command only allows erasure of all user sectors CRP3 0x43218765 access to chip via the JTAG pins is disabled If a valid user code is present in flash sector 0ISP entry by pulling PIO14 LOW...

Page 225: ...commands Set Baud Rate Write to RAM Read Memory and Go commands 25 9 1 Unlock unlock code Table 214 ISP command summary ISP Command Usage Described in Unlock U unlock code Table 215 Set Baud Rate B baud rate stop bit Table 216 Echo A setting Table 218 Write to RAM W start address number of bytes Table 219 Read Memory R address number of bytes Table 220 Prepare sector s for write operation P start ...

Page 226: ...ISP command handler compares it with the check sum of the received bytes If the check sum matches Table 216 ISP Set Baud Rate command Command B Input baud rate 9600 19200 38400 57600 115200 230400 stop bit 1 2 Return Code CMD_SUCCESS INVALID_BAUD_RATE INVALID_STOP_BIT PARAM_ERROR Description this command changes the baud rate The new baud rate is effective after the command handler sends the CMD_S...

Page 227: ...eck sum does not match the host must respond with RESEND CR LF In response the ISP command handler sends the data again Table 219 ISP Write to RAM command Command W Input start address RAM address where data bytes are to be written This address must be a word boundary number of bytes number of bytes to be written Count must be a multiple of 4 Return Code CMD_SUCCESS ADDR_ERROR Address not on word ...

Page 228: ...le sector use the same Start and End sector numbers Example P 0 0 CR LF prepares flash sector 0 Table 222 ISP Copy command Command C Input flash address DST destination flash address where data bytes are to be written Destination address must be a 256 byte boundary RAM address SRC source RAM address from where data bytes are to be read number of bytes number of bytes to be written Must be 256 512 ...

Page 229: ...LED Description executes a program residing in RAM or flash memory It cannot be possible to return to the ISP command handler once this command is successfully executed Blocked when code read protection is enabled Example G 0 A CR LF branches to address 0x0000 0000 in ARM mode Table 224 ISP Erase sector command Command E Input start sector number end sector number Must be greater than or equal to ...

Page 230: ...ocation INVALID_SECTOR PARAM_ERROR Description blank checks one or more sectors of on chip flash memory blank check on sector 0 always fails as first 64 bytes are remapped to flash boot block Example I 2 3 CR LF blank checks flash sectors 2 and 3 Table 226 ISP Read part identification number command Command J Input none Return Code CMD_SUCCESS followed by part identification number in ASCII see Ta...

Page 231: ...2 1073741824 4 CR LF compares 4 bytes from the RAM address 0x4000 0000 to the 4 bytes from the flash address 0x2000 Table 230 ISP Return codes summary Return code Mnemonic Description 0 CMD_SUCCESS command executed successfully Sent by ISP handler only when command given by the host has been completely and successfully executed 1 INVALID_COMMAND invalid command 2 SRC_ADDR_ERROR source address is n...

Page 232: ...ommand is received The IAP routine resides at 0x7FFF FFF0 location and is Thumb code The IAP function can be called in the following way using C Define the IAP location entry point Since the 0th bit of the IAP location is set there will be a change to Thumb instruction set when the program counter branches to this address define IAP_LOCATION 0x7ffffff1 Define data structure or pointers to pass IAP...

Page 233: ...s can be passed in registers r0 r1 r2 and r3 respectively Additional parameters are passed on the stack Up to 4 parameters can be returned in registers r0 r1 r2 and r3 respectively Additional parameters are returned indirectly via memory Some of the IAP calls require more than 4 parameters If the ARM suggested scheme is used for the parameter passing returning then it may create problems due to di...

Page 234: ...nd result table RESULT 1 RESULT 2 ARM REGISTER r1 RESULT n Table 232 IAP Prepare sector s for write operation command Command Prepare sector s for write operation Input command code 5010 param0 start sector number param1 end sector number must be greater than or equal to start sector number Return Code CMD_SUCCESS BUSY INVALID_SECTOR Result none Description execute before executing Copy RAM to Fla...

Page 235: ...n correct boundary SRC_ADDR_NOT_MAPPED DST_ADDR_NOT_MAPPED COUNT_ERROR byte count is not 256 512 1024 4096 SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION BUSY Result none Description programs flash memory Affected sectors must be prepared first by calling Prepare Sector for Write Operation command Affected sectors are automatically protected again once the copy command is successfully executed The boot s...

Page 236: ...f the status code is SECTOR_NOT_BLANK result1 contents of non blank word location Description blank checks a sector or multiple sectors of on chip flash memory To blank check a single sector use the same Start and End sector numbers Table 236 IAP Read part identification number command Command Read part identification number Input command code 5410 parameters none Return Code CMD_SUCCESS Result re...

Page 237: ...s must be a word boundary param1 SRC starting flash or RAM address of data bytes to be compared Address must be a word boundary param2 number of bytes to be compared must be a multiple of 4 Return Code CMD_SUCCESS COMPARE_ERROR COUNT_ERROR Byte count is not a multiple of 4 ADDR_ERROR ADDR_NOT_MAPPED Result result0 offset of the first mismatch if the status code is COMPARE_ERROR Description compare...

Page 238: ...ning off the PLL In such cases the ISP utility must pass the PLL frequency after autobaud handshake Another option is to disable the PLL before making this IAP call Remark TIMER1 registers must be programmed with reset values before Reinvoke ISP command is used Table 240 IAP status codes summary Status code Mnemonic Description 0 CMD_SUCCESS command is executed successfully 1 INVALID_COMMAND inval...

Page 239: ...chains within the ARM7TDMI S A JTAG style test access port controller controls the scan chains In addition to the scan chains the debug architecture uses EmbeddedICE logic which resides on chip with the ARM7TDMI S core The EmbeddedICE has its own scan chain that is used to insert watchpoints and breakpoints for the ARM7TDMI S core The EmbeddedICE logic consists of two real time watchpoint register...

Page 240: ...K can be driven HIGH externally or allowed to float HIGH via its on chip pull up To make them occur as GPIO pins do not connect a bias resistor and ensure that any external driver connected to Pin 26 RTCK is either driving high or is in high impedance state during reset Table 241 EmbeddedICE pin description Pin name Type Description TMS input test mode select TMS pin selects the next state in the ...

Page 241: ...register 0 0100 Debug Comms Data register 32 debug communication data register 0 0101 Watchpoint 0 Address Value 32 holds watchpoint 0 address value 0 1000 Watchpoint 0 Address Mask 32 holds watchpoint 0 address mask 0 1001 Watchpoint 0 Data Value 32 holds watchpoint 0 data value 0 1010 Watchpoint 0 Data Mask 32 holds watchpoint 0 data mask 0 1011 Watchpoint 0 Control Value 9 holds watchpoint 0 co...

Page 242: ...t driver is disabled until the internal wake up time has expired allowing an interval between the release of the external reset and the release of the internal reset during which RTCK can be driven by an external signal if necessary This procedure establishes the PIO27 to PIO31 pins as the JTAG test debug interface Pin connect block settings have no affect on PIO27 to PIO31 pins if they are initia...

Page 243: ...is being debugged Remark RealMonitor is a configurable software module which enables real time debug RealMonitor is developed by ARM Inc Information presented in this section is taken from the ARM document RealMonitor Target Integration Guide ARM DUI 0142A It applies to a specific configuration of RealMonitor software programmed in the on chip ROM boot memory of this device Refer to the white pape...

Page 244: ...or ethernet Angel is required to save and restore full processor context and the occurrence of interrupts can be delayed as a result Angel as a fully functional target based debugger is therefore too heavyweight to perform as a real time monitor Multi ICE is a hardware debug solution that operates using the EmbeddedICE unit that is built into most ARM processors To perform debug tasks such as acce...

Page 245: ...tails on RMTarget functionality see the RealMonitor Target Integration Guide ARM DUI 0142A 27 3 4 How RealMonitor works In general terms the RealMonitor operates as a state machine as shown in Figure 72 RealMonitor switches between running and stopped states in response to packets received by the host or due to asynchronous events on the target RMTarget supports the triggering of only one breakpoi...

Page 246: ...lication to continue running without stopping the processor RealMonitor considers the user application to consist of two parts a foreground application running continuously typically in User System or SVC mode a background application containing interrupt and exception handlers triggered by certain events in the user system including IRQs or FIQs Data and prefetch aborts caused by user foreground ...

Page 247: ...tack space The user must therefore allow sufficient stack space for both RealMonitor and application RealMonitor stack requirements are shown in Table 243 27 4 2 IRQ mode A stack for this mode is always required RealMonitor uses two words on entry to its interrupt handler These are freed before nested interrupts are enabled 27 4 3 Undef mode A stack for this mode is always required RealMonitor use...

Page 248: ... where an application has no exception handlers of its own the application can install the RealMonitor low level exception handlers directly into the vector table of the processor Although the IRQ handler must get the address of the Vectored Interrupt Controller The easiest way to do this is to write a branch instruction address into the vector table where the target of the branch is the start add...

Page 249: ...ess DCD __init Reset Entry point Undefined_Address DCD rm_undef_handler Provided by RealMonitor SWI_Address DCD 0 User can put address of SWI handler here Prefetch_Address DCD rm_prefetchabort_handler Provided by RealMonitor Abort_Address DCD rm_dataabort_handler Provided by RealMonitor FIQ_Address DCD 0 User can put address of FIQ handler here AREA init_code CODE ram_end EQU 0x4000xxxx Top of on ...

Page 250: ...entry is aware of the VIC and it enables the DBGCommRX and DBGCommTx interrupts Default vector address register is programmed with the address of Non vectored app_irqDispatch mentioned in this example User can set up Vectored IRQs or FIQs here VICBaseAddr EQU 0xFFFFF000 VIC Base address VICDefVectAddrOffset EQU 0x34 LDR r0 VICBaseAddr LDR r1 app_irqDispatch STR r1 r0 VICDefVectAddrOffset BL rm_ini...

Page 251: ...are of the VIC interrupt priority hardware so trick rm_irqhandler2 to return here STMFD sp ip pc LDR pc rm_irqhandler2 rm_irqhandler2 returns here MSR cpsr_c 0x52 Disable irq move to IRQ mode MSR spsr r12 Restore SPSR from r12 STMFD sp r0 LDR r0 VICBaseAddr STR r1 r0 VICVectAddrOffset Acknowledge Non Vectored irq has finished LDMFD sp r12 r14 r0 Restore registers SUBS pc r14 4 Return to the interr...

Page 252: ...WRITEBYTES TRUE RM_OPT_READHALFWORDS TRUE RM_OPT_WRITEHALFWORDS TRUE RM_OPT_READWORDS TRUE RM_OPT_WRITEWORDS TRUE Enables or disables support for 8 16 32 bit read write RM_OPT_EXECUTECODE FALSE Enables or disables support for executing code from execute code buffer The code must be downloaded first RM_OPT_GETPC TRUE This option enables or disables support for the RealMonitor GetPC packet Useful in...

Page 253: ...tion specifies the size in words of the data logging FIFO buffer CHAIN_VECTORS FALSE This option allows RMTarget to support vector chaining through µHAL ARM HW abstraction API 28 Abbreviations Table 244 Abbreviations Acronym Description ADC Analog to Digital Converter AMBA Advanced Microcontroller Bus Architecture APB ARM Peripheral Bus CPU Central Processing Unit DAC Digital to Analog Converter D...

Page 254: ...ual Rev 1 16 December 2011 254 of 268 NXP Semiconductors UM10413 MPT612 User manual SRAM Static Random Access Memory SSP Synchronous Serial Port TTL Transistor Transistor Logic UART Universal Asynchronous Receiver Transmitter VIC Vector Interrupt Controller WO Write Only Table 244 Abbreviations continued Acronym Description ...

Page 255: ...NXP Semiconductors products and NXP Semiconductors accepts no liability for any assistance with applications or customer product design It is customer s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer s applications and products planned as well as for the planned application and use of customer s third party customer s Customers should p...

Page 256: ...description 25 Table 26 FIQ Status register VICFIQStatus address 0xFFFF F004 bit allocation 26 Table 27 FIQ Status register VICFIQStatus address 0xFFFF F004 bit description 26 Table 28 Vector control registers 0 to 15 VICVectCntl0 to 15 0xFFFF F200 to 23C bit description 26 Table 29 Vector address registers 0 to 15 VICVectAddr0 to 15 addresses 0xFFFF F100 to 13C bit description 27 Table 30 Default...

Page 257: ... accessible register description 73 Table 81 UART0 pin description 76 Table 82 UART0 register map 77 Table 83 UART0 Receiver buffer register U0RBR address 0xE000 C000 when DLAB 0 read only bit description 78 Table 84 UART0 Transmit holding register U0THR address 0xE000 C000 when DLAB 0 write only bit description 78 Table 85 UART0 Divisor latch LSB register U0DLL address 0xE000 C000 when DLAB 1 bit...

Page 258: ... register I2SCLH I2C0 I2C0SCLH address 0xE001 C010 and I2C1 I2C1SCLH address 0xE005 C010 bit description 127 Table 128 I2C SCL low duty cycle register I2SCLL I2C0 I2C0SCLL address 0xE001 C014 and I2C1 I2C1SCLL address 0xE005 C014 bit description 127 Table 129 Example of I2C clock rates 128 Table 130 Abbreviations used to describe an I2C operation 128 Table 131 I2CONSET used to initialize master tr...

Page 259: ...85 Watchdog operating modes selection 200 Table 186 Watchdog mode register WDMOD address 0xE000 0000 bit description 200 Table 187 WatchDog timer constant register WDTC address 0xE000 0004 bit description 201 Table 188 Watchdog feed register WDFEED address 0xE000 0008 bit description 201 Table 189 WatchDog timer value register WDTV address 0xE000 000C bit description 201 Table 190 RTC pin descript...

Page 260: ... Fig 10 Slave mode operation of the on chip oscillator 37 Fig 11 External interrupt logic 42 Fig 12 PLL block diagram 45 Fig 13 Start up sequence diagram 53 Fig 14 Reset block diagram including the wake up timer54 Fig 15 APB Divider connections 56 Fig 16 LQFP48 pin configuration 57 Fig 17 Illustration of the fast and slow GPIO access and output showing a 3 5 increase of the pin output frequency 76...

Page 261: ...cle length of 100 selected by MR3 and MAT3 0 enabled as PWM outputs by register PWCON 196 Fig 57 A timer cycle in which PR 2 MRx 6 and both interrupt and reset on match are enabled 196 Fig 58 A timer cycle in which PR 2 MRx 6 and both interrupt and stop on match are enabled 197 Fig 59 Timer3 block diagram 198 Fig 60 Watchdog timer block diagram 202 Fig 61 RTC block diagram 203 Fig 62 RTC prescaler...

Page 262: ...ar register VICIntEnClear 0xFFFF F014 23 9 4 6 Interrupt select register VICIntSelect 0xFFFF F00C 24 9 4 7 IRQ Status register VICIRQStatus 0xFFFF F000 25 9 4 8 FIQ Status register VICFIQStatus 0xFFFF F004 25 9 4 9 Vector control registers 0 to 15 VICVectCntl0 15 0xFFFF F200 to 23C 26 9 4 10 Vector address registers 0 to 15 VICVectAddr0 to 15 0xFFFF F100 to 13C 26 9 4 11 Default vector address reg...

Page 263: ...ct register values 66 13 General Purpose Input Output GPIO ports 66 13 1 Features 66 13 2 Applications 67 13 3 Pin description 67 13 4 Register description 67 13 4 1 GPIO Direction register IODIR IO0DIR 0xE002 8008 FIODIR FIO0DIR 0x3FFF C000 68 13 4 2 Fast GPIO mask register FIOMASK FIO0MASK 0x3FFF C010 69 13 4 3 GPIO Pin value register IOPIN IO0PIN 0xE002 8000 FIOPIN FIO0PIN 0x3FFF C014 70 13 4 4...

Page 264: ...re 113 16 I2C interfaces I2C0 and I2C1 114 16 1 Features 114 16 2 Applications 115 16 3 Description 115 16 4 Pin description 116 16 5 I2C operating modes 116 16 5 1 Master transmitter mode 116 16 5 2 Master receiver mode 117 16 5 3 Slave receiver mode 118 16 5 4 Slave transmitter mode 119 16 6 I2C implementation and operation 119 16 6 1 Input filters and output stages 119 16 6 2 Address register I...

Page 265: ... State 0xB0 150 16 9 9 3 State 0xB8 150 16 9 9 4 State 0xC0 150 16 9 9 5 State 0xC8 150 17 SPI Interface SPI0 151 17 1 Features 151 17 2 Description 151 17 2 1 SPI overview 151 17 2 2 SPI data transfers 151 17 2 3 General information 153 17 2 4 Master operation 153 17 2 5 Exception conditions 154 17 2 6 Read overrun 154 17 2 7 Write collision 154 17 2 8 Mode fault 154 17 2 9 Slave abort 154 17 3 P...

Page 266: ... 5 6 Prescale counter register PC TIMER1 T1PC 0xE000 8010 183 21 5 7 Match registers MR0 MR3 183 21 5 8 Match control register MCR TIMER1 T1MCR 0xE000 8014 183 21 5 9 Capture registers CR0 CR3 184 21 5 10 Capture control register CCR TIMER1 T1CCR 0xE000 8028 184 21 5 11 External match register EMR TIMER1 T1EMR 0xE000 803C 185 21 5 12 PWM Control register PWMCON TIMER1 PWM1CON 0xE000 8074 186 21 5 ...

Page 267: ...programming 217 25 1 Introduction 217 25 2 Boot loader 217 25 3 Features 217 25 4 Applications 217 25 5 Description 217 25 5 1 Memory map after any reset 218 25 5 2 Criterion for valid user code 218 25 5 3 Communication protocol 219 25 5 4 ISP command format 219 25 5 5 ISP response format 219 25 5 6 ISP data format 219 25 5 7 ISP flow control 220 25 5 8 ISP command abort 220 25 5 9 Interrupts duri...

Page 268: ...1 26 8 Debug mode 241 26 8 1 Enable debug mode 242 26 8 2 JTAG pin selection 243 27 RealMonitor 243 27 1 Features 243 27 2 Applications 243 27 3 Description 244 27 3 1 RealMonitor components 244 27 3 2 RMHost 245 27 3 3 RMTarget 245 27 3 4 How RealMonitor works 245 27 4 How to enable RealMonitor 247 27 4 1 Adding stacks 247 27 4 2 IRQ mode 247 27 4 3 Undef mode 247 27 4 4 SVC mode 247 27 4 5 Prefe...

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