NXP Semiconductors ADC1002S020 Quick Start Manual Download Page 10 | Manualshive

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NXP Semiconductors

Quick Start ADC1002S020

QS ADC1002S020

QS_ADC1002S020_2

© NXP B.V. 2010. All rights reserved.

Quick Start

Rev. 2 — 11 octobre 2010

10 of 24

•

or the clock provided by the ADC refer to as P1_CLK_IN. This is the preferred

situation since the user will not deal with any set-up/hold timing for the acquisition.

Refer to

section 3.2

for software configuration.

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Summary of Contents for ADC1002S020

Page 1: ...1 octobre 2010 Quick Start Document information Info Content Keywords DEMO8766G PCB769 2 Demonstration board ADC Converter ADC1002S020 Abstract This document describes how to use the demonstration board DEMO8766G for the analog to digital converter ADC1002S020 Overview ...

Page 2: ...aimers NXP B V 2010 All rights reserved Quick Start Rev 2 11 octobre 2010 2 of 24 Contact information For additional information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com Revision history Rev Date Description 1 20080612 Initial version 2 20101011 Update for data acquisition system ...

Page 3: ...ased on DEMO8766G Fig 1 ADC1002S020 demoboard set up POWER SUPPLY I 50 mA 12 V GND LOGIC ANALYZER Output data D9 MSB to D0 LSB CLOCK SIGNAL sinewave AC SYNTHESIZED SIGNAL GENERATOR INPUT SIGNAL 2 Vpp sinewave AC SYNTHESIZED SIGNAL GENERATOR FILTER High order Band pass PRESENTED CONFIGURATION 2Vpp input full scale Single TTL CMOS clock signal 3 3 V power supply ADC active Binary ADC output VRB 1 2 ...

Page 4: ...ion K3 3 3 V 5 V TP31 VCC test point ADC power supply TM1 TM2 MASSE test point Analog ground TM3 TM4 GND test point Digital ground STDBY switch ADC stand by activation K2 ADC active ADC OFF 1 3 DC voltage adjustments The ADC1002S020 allows to adjust the full scale input signal from 1 6 V to 2 4 V Table 2 DC voltage adjustments Name Function View P1 VRT trimmer TOP reference adjustment TP1 VRT test...

Page 5: ...Msps should follow the formula where M is an odd number of period and N is the number of samples Table 3 Input signals Name Function View J2 VI connector Analog input signal 50Ω matching J3 CLK connector Clock input signal 50Ω matching 1 5 Output signals D0 to D9 IR Table 4 Output signals Name Function View TP10 to TP30 Array connector ADC digital output D0 to D9 and In range signal IR DS1 IR gree...

Page 6: ...uisition board Fig 2 HSDC extension module acquisition board 5V POWER SUPPLY I 3 2 A REFERENCE SIGNAL typical 10 MHz SIGNAL GENERATOR USB SPI MODULE PRESENTED CONFIGURATION acquisition board external reference signal LVDS DDR 16 bit input stream CMOS 2 16 bit channels input LVDS DDR I O CONNECTOR up to 325 MHz 16 bit LVDS DDR CMOS I O CONNECTOR 2 channels up to 200 MHz 16 bit JUMPER FOR I O SUPPLY...

Page 7: ...n In this section the specific requirement for the use with ADC1002S020 demo board will be shown For more details on the HSDC EXTMOD01 DB please contact dataconverter support nxp com 2 1 HSDC extension module hardware initialization Before using the generation board make sure that you connect the USB cable prior to the supply 2 2 HSDC extension module software initialization Before using the gener...

Page 8: ...4 USBConfigSetup window step 2 Click Next to continue Fig 5 USBConfigSetup window step 3 Click Next to finish the installation process The system is now ready to use the ADC1412D series board for evaluation purpose 2 3 HSDC extension module CMOS connector description The figure 6 shows a brief description of the hardware connection on the HE14 connector ...

Page 9: ... of 24 Fig 6 HSDC extension module HE14 CMOS hardware schematic overview The HSDC extension module can acquire data in CMOS level using either the on board clock generated by the internal PLL refer to as pDFS_CLK 0 nDFS_CLK 0 that will be used by the FPGA In this case the reference of the board should be delivered by the clock signal generator ...

Page 10: ... V 2010 All rights reserved Quick Start Rev 2 11 octobre 2010 10 of 24 or the clock provided by the ADC refer to as P1_CLK_IN This is the preferred situation since the user will not deal with any set up hold timing for the acquisition Refer to section 3 2 for software configuration ...

Page 11: ...HSDC ACC07 DB The measurement set up presented below shows 1 generator for input signal Clock signal is delivered by the HSDC EXTMOD for ADC clocking and data acquisition purpose Fig 7 Evaluation set up measurement with ADC1002S020 and HSDC EXTMOD01 DB USB SPI MODULE PRESENTED CONFIGURATION Single ended clock on CLK 2 Vpp input full scale Signal generator synchronized with HSDC EXTMOD CLOCK SIGNAL...

Page 12: ... status field Flash the FPGA with the appropriate bin file provided on the CD located at HSDC EXTMOD01 Software USBConfigSetup v1 3 100212 1525 HSDCEXTMOD FPGA bin v03 Among the 8 files 2 are considered here HSDCEXTMOD_v03_P1C_RE_3V3_GEN bin the FPGA will use the rising edge of the clock delivered by connector P1C HSDCEXTMOD _v03_P1C_FE_3V3_ACQ bin the FPGA will use the falling edge of the clock d...

Page 13: ...nding frequency being actually generated by the board The Data Phase Shift allows the user to shift the clock position wrt data by the amount of time indicated Note you can edit the LMK file by clicking on the Edit button to define your own frequency as long as you respect the frequency range defined by the PLL For other frequencies to generate please contact dataconverter support nxp com for more...

Page 14: ...or ADC1002S020 3 4 1 Pattern acquisition Browse on both channel path configuration to select the file to store the data that will be acquired Click on Acquire and Save buttons to end the capture process 3 5 FFT post processing Once acquisition is done the captured data can now be processed for FFT results using the NXP_ADC_Acquisition exe tool located under directory HSDC EXTMOD01 Software NXP_ADC...

Page 15: ...frequency Indicate CMOS mode 3 5 2 Acquisition software frequency indication The second step consists in indicating the relevant numbers for the FFT processing the resolution N 10 in this case the input frequency Fin 1 25 MHz in our example the sampling frequency Fs 20 Msps in our example whether Fin or Fs are coherent or not if signals are coherent selected which Fin or Fs are fixed for the calcu...

Page 16: ...3 5 3 Acquisition software FFT results display Press the COMPUTE button to display the results from the FFT processing The results fields will be updated depending on the number of input files If 2 files have been processed it is possible to display both results on the same picture for all graphs using the Display button Display ADC1 or Display ADC2 or Display ADC1 ADC2 3 5 3 1 FFT spectrum The fi...

Page 17: ...display the whole content The tables and give the relevant dynamic parameters Table first 6 harmonics frequencies and amplitude level Table dynamics parameters ENOB expressed in bit Level of the digital output signal relative to the full scale SINAD in dBc THD in dBc calculated over first 6 harmonics SNR in dBc and dBFS SFDR in dBc and dBFS 3 5 3 2 Reorganized signal The Reorganized signal display...

Page 18: ...010 All rights reserved Quick Start Rev 2 11 octobre 2010 18 of 24 Fig 14 NXP_ADC_Acquisition window reorganized signal Press the Autoscale button to display the whole content 3 5 3 3 Unreconstruted signal The unreconstructed signal displays the unreconstructed sine wave corresponding to the whole number of period being acquired following the coherency rule ...

Page 19: ... 2 11 octobre 2010 19 of 24 Fig 15 NXP_ADC_Acquisition window unreconstruted signal Press the Autoscale button to display the whole content Use the zoom tool to observe in more details all the captured data 3 5 3 4 Histogram The histogram graph shows the distribution of output codes This graph allows to know which code is present and if there is any missing code in the conversion range Zoom tool ...

Page 20: ...ation provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Quick Start Rev 2 11 octobre 2010 20 of 24 Fig 16 NXP_ADC_Acquisition window code histogram Press the Autoscale button to display the whole content The table shows the range of output codes ...

Page 21: ...th Fin Fs and N known M has to be chosen such that it follows the equation above To do this iterative calculation one has to decide whether Fin or Fs is fixed To illustrate this process let s consider our current example with Fin 1 MHz Fs 20 Msps and N 8192 samples acquired if Fin is fixed this leads to M 409 periods of input signal to be acquired and a real sampling frequency to be Fs 20 0293399 ...

Page 22: ...C1002S020_2 All information provided in this document is subject to legal disclaimers NXP B V 2010 All rights reserved Quick Start Rev 2 11 octobre 2010 22 of 24 5 Notes For any question feel free to contact us at the following e mail dataconverter support nxp com ...

Page 23: ...design It is customer s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer s applications and products planned as well as for the planned application and use of customer s third party customer s Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products NXP Semi...

Page 24: ... 6 2 1 HSDC extension module hardware initialization7 2 2 HSDC extension module software initialization 7 2 3 HSDC extension module CMOS connector description 8 3 Combo ADC1002S020 and HSDC extension module 11 3 1 Measurement set up overview 11 3 2 HSDC extension module FPGA flash 12 3 3 HSDC extension module DATA clock configuration 12 3 4 HSDC extension module pattern acquisition 13 3 4 1 Patter...

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