NXP Semiconductors
Quick Start ADC1002S020
QS ADC1002S020
QS_ADC1002S020_2
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Quick Start
Rev. 2 — 11 octobre 2010
13 of 24
Fig 9. “USB Configurator” window: DATA clock configuration
The FPGA configuration indicates which configuration file has been programmed in
FPGA, in the example shown it is the rising edge of the embedded clock.
In the directory “\HSDC-EXTMOD01\Software\USBConfigSetup v1.3 100212
1525\Config” of the CD, there are 2 configurations files that already defines frequencies
for the DFS and AFS (AQM clock configuration that we don’t use here). Copy these files
to the directory “C:\Documents and Settings\All Users\Application Data\Electronique
Concept\UsbConfig” to get access to these frequencies.
Select “LMK03001 20 MHz – 20 MHz (20.000 MHz)” to define the frequency to be 20
MHz. The pattern will be acquired as this sampling rate, meaning 20 MHz CMOS.
Click “Update”, this should display 6 green check boxes and the value of the
corresponding frequency being actually generated by the board.
The Data Phase Shift allows the user to shift the clock position wrt data by the amount of
time indicated.
Note: you can edit the LMK file by clicking on the “Edit…” button to define your own
frequency, as long as you respect the frequency range defined by the PLL. For other
frequencies to generate, please contact
for more
details.
3.4 HSDC extension module: pattern acquisition
The clock frequency is defined, and the board is ready to acquire the pattern.
In order to do the acquisition, the number of samples needs to be filled in the Pattern size
field: this number is a power of 2 with a maximum of 8MB.
Select one-shot mode and source P1 to acquire data (see
figure 10
).
The hardware connection between the ADC1002S020 and the HSDC extension module
has to be described to get correct results. This is done by using the fields in “Channel 0
Input Configuration” and in “Channel 1 Input Configuration”.
The channel 0 receives the data from ADC where ADC MSB is connected to the 1
st
bit
and ADC LSB is connected to the 10
th
bit of the HSDC extension module. Tune the fields
“Input is located on file A between xx (MSB) and xx (LSB)” to describe this configuration
(see
figure 10
).
