Novatel HS 3001, Integration Manual

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Engineering Layer Stack-up And Impedance
Layer Line Width/Space (mil) Control Impedance (
Ω
)
L1 51.18/24 mil 50 ± 10%
L1 1 oz +plating
CORE 0.3 11.81mil
L2 1 oz
PP 3313 3.3003mil
CORE 0.6 23.62mil
PP 3313 3.3198mil
L3 1 oz
CORE 0.3 11.81mil
L4 1 oz +plating
Overlap THK: 1.47 mm Material : FR4 IT-180A
Finish THK: 1.6 ± 0.16 mm
Layer LW/LS(mil) Calculate Value (
Ω
) H1(mil)Er1 H2(mil)Er2
L1 55/22.09 mil ± 5% 50.6 (coplanar waveguide) 43.3 ± 5% 4.24
L3 Ground
V
BAT
Input
The HS 3001 V
BAT
input can have a relative high current draw that can fluctuate rapidly,
especially when transmitting at max power and burst mode. The V
BAT
interface must be
designed to provide the required instantaneous voltage and current with minimal voltage
droop. This includes both sufficient bulk decoupling capacitance as well as adequate layout
provisions.
When laying out the connections to the cellular module interface connector, it is tempting to
use traces of the same width as the connector pins. However, this is a very compact connector
and traces of that width will not have sufficient copper. Similar to the discussion on thermal
relief, the use of narrow traces to connect the V
BAT
pins to the source voltage can act like a
high impedance and cause a significant voltage droop when higher currents are required.
If the V
BAT
drops too low, the cellular modules will reset. To minimize the trace loss, use a
larger trace that spans several pins. Any concern about solderability can be mitigated by
using a solder mask with cutouts for the individual pins as shown in the figure below. The
layout should provide sufficient trace width over the entire trace from the Enable modules all
the way to the source of the V
BAT
voltage. Any transitions between layers for this trace should
use multiple vias.