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North Atlantic 75DS2, Operation Manual

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North Atlantic 75DS2 Operation Manual Download Page 29

 

  

2/4 Ch DLV (5*) (PCI) MODULE MEMORY MAP 

  

75DS2 Operations Manual

 

North Atlantic Industries, Inc.

 

11/11/2011

 

Rev: 2011-11-11-1000 

www.naii.com

 

Page 29 of 43 

 

2/4

 

C

H 

DLV

 

(5*)

 

(PCI)

 

MODULE

 

MEMORY

 

MAP 

 

000  Wrap DLV Position Lo CH1A 

R 

140 

DLV Set Excitation Volt Lo CH1 

W/R  310 

DLV Write Position Lo CH2A 

W/R 

004  Wrap DLV Position Hi CH1A 

R 

144 

DLV Set Excitation Volt Hi CH1 

W/R  314 

DLV Write Position Hi CH2A 

W/R 

008  Wrap DLV Position Lo CH2A 

R 

148 

DLV Set Excitation Volt Lo CH2 

W/R  318 

DLV Write Position Lo CH2B 

W/R 

00C  Wrap DLV Position Hi CH2A 

R 

14C  DLV Set Excitation Volt Hi CH2 

W/R  31C  DLV Write Position Hi CH2B 

W/R 

010  Wrap DLV Position Lo CH1B 

R 

 

 

 

 

 

 

014  Wrap DLV Position Hi CH1B 

R 

160 

DLV Set Signal Volt Lo CH1 

W/R  330 

OSC Set Voltage Lo 

W/R 

018  Wrap DLV Position Lo CH2B 

R 

164 

DLV Set Signal Volt Hi CH1 

W/R  334 

OSC Set Voltage HI 

W/R 

01C  Wrap DLV Position Hi CH2B 

R 

168 

DLV Set Signal Volt Lo CH2 

W/R  338 

OSC Set Frequency Lo 

W/R 

 

 

 

16C  DLV Set Signal Volt Hi CH2 

W/R  33C  OSC Set Frequency Hi  

W/R 

064  DLV Channel Excitation Voltage CH1  R 

 

 

 

 

 

 

068  DLV Channel Excitation Voltage CH2  R 

180 

DLV BIT Test Enable 

W/R  700 

DLV Status, BIT Test  

R 

070  DLV Channel Signal Voltage CH1 

R 

188 

D2 Test Verify 

W/R  704 

Excitation Loss Interrupt Enable 

W/R 

074  DLV Channel Signal Voltage CH2 

R 

18C  DLV Output Mode 

W/R  708 

Signal Loss Interrupt Enable 

W/R 

 

 

 

198 

DLV 2 or 4-Wire Select Mode 

W/R  70C  BIT FAIL Interrupt Enable 

W/R 

080  Signal Loss Threshold CH1 

W/R  1C0  DLV Module Power Enable 

W/R  710 

Phase Lock Loss Interrupt Enable 

W/R 

084  Signal Loss Threshold CH2 

W/R  1C8  DLV Active Channel Select 

W/R   

 

 

08C  Excitation Loss Threshold CH1 

W/R  1CC  DLV Status, Excitation Loss 

R 

768 

Module Design Version 

R 

090  Excitation Loss Threshold CH2 

W/R  1D0  DLV Phase Lock Status CH1/2 

R 

76C  Module Design Revision 

R 

 

 

 

 

 

 

770 

Module DSP Revision 

R 

098  Channel 1 Frequency 

R 

1E8  DLV Set Phase Offset CH1 

W/R  774 

Module FPGA Revision 

R 

09C  Channel 2 Frequency 

R 

1EC  DLV Set Phase Offset CH2 

W/R  778 

Module ID Revision 

R 

 

 

 

 

 

 

 

 

 

0B0  Status, Signal Loss 

R 

300 

DLV Write Position Lo CH1A 

W/R  7C0  Vector Interrupt BIT Fail 

W/R 

 

 

 

304 

DLV Write Position Hi CH1A 

W/R  7C4  Vector Interrupt EXC Loss 

W/R 

0D8  DLV Response / Filter Time CH1 

W/R  308 

DLV Write Position Lo CH1B 

W/R  7C8  Vector Interrupt Signal Loss 

W/R 

0DC  DLV Response / Filter Time CH2 

W/R  30C  DLV Write Position Hi CH1B 

W/R  7CC  Vector Interrupt Phase Lock Loss 

W/R 

 

Summary of Contents for 75DS2

Page 1: ...75DS2 Operations Manual North Atlantic Industries Inc 11 11 2011 Rev 2011 11 11 1000 www naii com Page 1 of 43 75DS2 3U cPCI SYNCHRO RESOLVER or LVDT RVDT CONVERTER OPERATIONS MANUAL ...

Page 2: ...oard which incorporates up to 4 Digital to Synchro Resolver converters with 1 5 2 2 or 3 VA drive capability or 2 or 4 isolated DLV converters The board features continuous background BIT testing reference and signal loss detection Each channel is independent isolated and enables the user to ground one of the outputs without affecting performance This model drives passive or active loads In additi...

Page 3: ... Select Internal External Pending 12 D S Status External Amplifier Pending 12 D S Write Angle Single Speed 12 D S Write Angle Two Speed 12 D S Rotation 13 D S Stop Angle 13 D S Set Rotation Rate 13 D S Rotation Mode Continuous or Start Stop 13 D S Rotation Status 13 Start Rotation 13 Stop Rotation 13 D S Set Reference Voltage 14 D S Set Signal Voltage 14 D S BIT Test Enable 14 D S Status BIT Test ...

Page 4: ...Frequency 26 OSC Onboard Excitation Set Voltage 26 DLV Status BIT Test 27 Excitation Loss Interrupt Enable 27 Signal Loss Interrupt Enable 27 BIT Test Fail Interrupt Enable 27 Phase Lock Loss Interrupt Enable 27 Interrupt Vector 28 2 4 CH DLV 5 PCI MODULE MEMORY MAP 29 OPTIONAL ONBOARD REFERENCE CONTROL 30 OSC Optional Onboard Reference Supply Set Frequency 30 OSC Optional Onboard Reference Supply...

Page 5: ...5DS2 Operations Manual North Atlantic Industries Inc 11 11 2011 Rev 2011 11 11 1000 www naii com Page 5 of 43 Single Channel D S Module Code Table 41 2 4 Channel DLV Module Code Table 42 REVISION PAGE 43 ...

Page 6: ... programmable Start and Stop angles 0 to 13 6 RPS with a resolution of 0 15 sec Step size is 16 bits 0 0055 up to 1 5 RPS then linearly increases to 12 bits 0 088 at 13 6 RPS Reference Input Voltage 2 to 115Vrms Galvanic isolated Uses 1 ma max Channel Reference Frequency 47 Hz to 10 KHz See part number Phase Shift 0 5 max Between output and reference Programmable Phase Shift Programmable 90 with 0...

Page 7: ... system ground Weight 1 5 oz 42 g DLV Module 5 Two Four Isolated DLV Simulation Ch LVDT RVDT Outputs See P N Applies to each channel unless noted otherwise Number of Channels 2 3 4 wire 4 2 wire Resolution 16 bits 001526 FS Linearity 0 1 FS Output Gain 0 1 Output Format Configurable for either 3 4 wire or 2 wire Galvanically isolated Output voltage is programmable fixed or ratio metric Output Volt...

Page 8: ...e output option in P N option selection Improved version to 5 VA introduced DOM 6 11 Vrms to 28 Vrms Programmable with a resolution of 0 1 V 2 0 to 10 0 Vrms 47 Hz to 20 KHz frequency range 10 1 to 28 0 Vrms 47 Hz to 10 KHz frequency range or 115 Vrms fixed 115 0 Vrms 47 Hz to 2 0 KHz frequency range Accuracy No Load 2 of setting 10 KHz 5 of setting 10 KHz Regulation 10 No Load to Full Load Output...

Page 9: ...ule memory map The memory map of each selected module counts from or is superimposed over its respective module offset Thus Address Base Module Offset Register Offset For example if a Digital I O module were selected to populate module 1 and a Discrete I O module were selected to populate module 2 Address Base Module 1 Offset 000 Digital I O register 010 Base 010 hex Address Base Module 2 Offset 8...

Page 10: ... and carrier frequency The module s extensive programmability now includes format selection synchro or resolver A background calibration feature pending that is totally transparent to the operation of the channels constantly adjusts outputs for all load and environmental conditions Each channel can be programmed for a different output voltage which can be programmed for either ratio metric or abso...

Page 11: ...Loss Threshold Each individual channel input signal voltage VL L is measured and the value reported to a corresponding read register The signal loss detection circuitry can be tailored to report a signal loss at Signal Loss Status register at a user defined threshold This threshold can be set to a resolution of 10 mv rms Program the threshold by writing the value of the voltage threshold in intege...

Page 12: ...8 D7 D6 D5 D4 D3 D2 D1 D0 Wrap Select Internal External X X X X X X X X X X X X X X CH2 CH1 D S Status External Amplifier Pending This monitors the external amplifier BIT signal See pin out Check the corresponding BIT status of the register for each active channel that has the external amplifier enabled connected A 1 BIT OK 0 BIT Fail D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Status Ex...

Page 13: ...sponding Set Rotation Rate registers Hi and Lo a 2 s complement number representing the desired rotation rate LSB 0 015 sec Ex 12 RPS 12 x 360 0 015 288000 46500h 12 RPS 12 x 360 0 015 288000 0xB9B00h Step size is 16 bits 0 0055 for up to 1 5 RPS and then linearly decreases to 12 bits 0 088 at 13 6 RPS D S Rotation Mode Continuous or Start Stop For continuous rotation set the corresponding channel...

Page 14: ... is totally transparent to the user requires no external programming and has no effect on the standard operation of this card Note Outputs must be ON and Reference supplied for test to function Card will write 55h every 0 1 seconds to the D S Test D2 Verify register when D2 is enabled User can periodically clear to 00h and then read the D S Test D2 Verify register again after 0 1 seconds to verify...

Page 15: ...r to be re written during next status update which when the channel is set INACTIVE should clear the fault Once this is done the front panel BIT LED will extinguish as long as the channels that are active are working properly and the channels not being utilized are set INACTIVE Note When D S Wrap Select External Internal register is set for external the BIT wrap will be read from the external ampl...

Page 16: ...3 D2 D1 D0 Trigger Source Select X X X X X X X X X X D X D X X D D S Trigger Slope Select May be used during implementation of D S rotation when D S Trigger Source Select register is set for external For rotation trigger on positive slope set the corresponding channel bit to 0 in the Trigger Slope Select register For negative slope set the bit to 1 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D...

Page 17: ...X X X X X X CH2 CH1 D S Status Phase Lock Loss Check the corresponding bit of the D S Phase Lock Loss Register for condition of the phase lock between the reference input and signal output for each active channel A 1 means Phase Lock Loss has occurred 0 means Phase Lock okay on active channels D S Active Channel Select Register Channels that are inactive are also set to 0 Phase Lock loss is detect...

Page 18: ... Loss will trigger an interrupt Default is 0 to disable interrupt on all channels When Status Interrupt is enabled Status Interrupt is reported through the Phase Lock Loss Interrupt Vector D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Phase Lock Loss Interrupt Enable X X X X X X X X X X X X X X CH2 CH1 OSC Optional Onboard Reference Supply Set Frequency Type 16 bit unsigned integer Range 4...

Page 19: ... 08 0 04 0 02 0 01 approximate value REF FREQUENCY LO D D D D D D D D D D D D D D D D D DATA BIT Hz REGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 approximate value REF FREQUENCY HI D D D D D D D D D D D D D D D D D DATA BIT Hz Interrupt Vector The Interrupt Vector Registers store the vectors for the specific interrupts generated by the modu...

Page 20: ...4 Stop Rotation CH2 W 090 Reference Loss Threshold CH2 W R 180 D S BIT Test Enable W R 184 D S Ratio 1 2 W R 700 D S Status BIT Test R 098 Channel 1 Frequency R 188 D2 Test Verify W R 704 Reference Loss Interrupt Enable W R 09C Channel 2 Frequency R 18C D S Output Mode W R 708 Signal Loss Interrupt Enable W R 0B0 Status Signal Loss R 190 D S Rotation Mode W R 70C BIT FAIL Interrupt Enable W R 198 ...

Page 21: ...round BIT testing on line that checks the output accuracy of each channel by comparing the measured output position to the commanded position This test continuously checks each channel individually over the programmed signal range to an accuracy of 0 2 FS Each DLV Signal output and Excitation input is continually monitored Any failure triggers an Interrupt if enabled and the results are available ...

Page 22: ...oss voltage threshold is to be 7 VRMS the programmed word to the corresponding register would be 700 2BCh Excitation Loss Threshold Each individual channel input excitation voltage VEXC is measured and the value reported to a corresponding read register The excitation loss detection circuitry can be tailored to report a excitation loss at EXC Status Ch 1 4 at a user defined threshold This threshol...

Page 23: ...5 D4 D3 D2 D1 D0 FUNCTION SIGNAL STATUS X X X X X X X X X X X X X X Ch2 Ch1 CHANNEL STATUS BIT DLV Channel Frequency Each individual channel excitation frequency is measured and the value reported to a corresponding read register The input excitation frequency is reported to a resolution of 1 Hz The output is in integer decimal format For example if channel 1 input excitation is 400 Hz the output ...

Page 24: ... to the D3 bit of the DLV Test Enable Register initiates a BIT Test that generates and tests 72 different positions to an accuracy of 0 05 External excitation is required and outputs must be ON The DLV Status bits will be set to indicate an accuracy problem Results are available in the DLV Test Status Registers and if enabled an interrupt will be generated See Interrupt Register Test cycle takes a...

Page 25: ...be monitored during BIT testing in the Active Channel register for the particular DLV channel 1 Active 0 not used IMPORTANT Omitting this step will produce false alarms because unused channels will set faults D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Active Channels X X X X X X X X X X X X X X CH2 CH1 DLV Status Excitation Loss Check the corresponding bit of the DLV Excitation Status r...

Page 26: ...4 D3 D2 D1 D0 FUNCTION 0 0 0 0 0 0 0 0 0 0 0 0 5242 88 2621 44 1310 72 655 36 approximate value REF FREQUENCY HI D D D D D D D D D D D D D D D D D DATA BIT Hz OSC Onboard Excitation Set Voltage Type 16 bit unsigned integer Range 2 0 to 28 0 Vrms or 115 Vrms Read Write R W Initialized Value N A Program Reference Voltage where LSB is 0 01 Vrms For example To program 26 1 Vrms 26 1 x 100 2610 which e...

Page 27: ...ult is 0 to disable interrupt on all channels When Status Interrupt is enabled Status Interrupt is reported through the Excitation Loss Interrupt Vector D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Excitation Loss Interrupt Enable X X X X X X X X X X X X X X CH2 CH1 Signal Loss Interrupt Enable Set the bit to enable interrupts for the corresponding channel When enabled a signal input loss...

Page 28: ...l interrupts If unique vectors are loaded into the registers a different Interrupt Service Routine ISR can be invoked by each interrupt The Signal Loss interrupt vector will be serviced when the Signal Loss status is set and the interrupt has been enabled The Reference Loss interrupt vector will be serviced when the Reference Loss status is set and the interrupt has been enabled The BIT interrupt ...

Page 29: ...DLV BIT Test Enable W R 700 DLV Status BIT Test R 070 DLV Channel Signal Voltage CH1 R 188 D2 Test Verify W R 704 Excitation Loss Interrupt Enable W R 074 DLV Channel Signal Voltage CH2 R 18C DLV Output Mode W R 708 Signal Loss Interrupt Enable W R 198 DLV 2 or 4 Wire Select Mode W R 70C BIT FAIL Interrupt Enable W R 080 Signal Loss Threshold CH1 W R 1C0 DLV Module Power Enable W R 710 Phase Lock ...

Page 30: ...tional Onboard Reference Supply Set Voltage Type Two 16 bit unsigned integer Range 2 0 to 28 0 Vrms or 115 Vrms Read Write R W Initialized Value 0 Program Reference Voltage where LSB is 0 01 Vrms For Example 26 1 Vrms 0x0A32 Reference Module is Optional REGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION 25 6 12 8 6 4 3 2 1 6 0 8 0 4 0 2 0 1 approximate value OSC SET VOLTAGE X ...

Page 31: ...art Number Read as a 16 bit binary word A unique 16 bit code is assigned to each model number Serial Number Read as a 16 bit binary word Date Code Read as a decimal number The four digits represent YYWW Year Year Week Week Revisions Read as a 16 bit binary word Board Ready Poll register Board is ready to be accessed only after you read AA55 Within 1 second after board power on Watchdog Timer This ...

Page 32: ...e together 4453h REGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION MODEL D D D D D D D D D D D D D D D D D DATA BIT ASCII C ASCII Generation This register holds product generation code 2 in ASCII Find ASCII 2 is in upper byte and ASCII space in lower byte together 3220h REGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION GENERATION D D D D D D D D D D D D ...

Page 33: ...an interrupt is not pending the least significant bit will be zero and the remaining bits will be unknown If it is read while an interrupt is pending the least significant bit will be 1 and bits 15 8 will contain the interrupt vector number Reading this register clears it and prepares for the next interrupt As such the interrupt service routine must read it only once per interrupt Because the inte...

Page 34: ...005 This mating connector may be purchased separately under NAI P N 05 0118 contact factory Rear Panel Connectors J1 J2 J1 cPCI interface only J2 I O defined see module slot pin out configuration Optional Onboard Reference Output Front Panel Rhi Out J4 pin 21 Rlo Out J4 pin 46 Rear Panel Rhi Out J2 pin D21 Rlo Out J2 pin D20 PIN 25 PIN 50 PIN 26 PIN 1 Reference Connector Key Slot Front Panel LEDs ...

Page 35: ... Ch 1 S2 Ch 2 S2 Ch 2 B Hi 9 E10 Ch 2 S4 Ch 2 B Lo 10 D5 Ch 2 RHi Ch 2 Exc Hi 35 D6 Ch 2 RLo Ch 2 Exc Lo 31 C7 Ch 2 Sense S1 32 C9 Ch 1 Sense S4 Ch 2 Sense S3 33 C8 Ch 1 Sense S2 Ch 2 Sense S2 34 C10 Ch 2 Sense S4 21 D21 RHI OUT RHI OUT RHI OUT 22 B21 12V Ext 12V Ext 12V Ext 23 F1 GND GND GND 24 B19 12V Ext 12V Ext 12V Ext 25 TRIG1 TRIG1 TRIG1 B3 Ch 1 EXT SIN HI B2 Ch 1 EXT COS HI B1 Ch 1 EXT GND ...

Page 36: ...0 D17 Ch 4 RHi Ch 4 Exc Hi 45 D18 Ch 4 RLo Ch 4 Exc Lo 41 C19 Ch 4 Sense S1 42 C21 Ch 2 Sense S4 Ch 4 Sense S3 43 C20 Ch 2 Sense S2 Ch 4 Sense S2 44 C18 Ch 4 Sense S4 46 D20 RLO 0UT RLO 0UT RLO 0UT 47 A21 12V Ext 12V Ext 12V Ext 48 F2 GND GND GND 49 A19 12V Ext 12V Ext 12V Ext 50 TRIG1 TRIG1 TRIG1 B11 Ch 3 EXT SIN HI B10 C h3 EXT COS HI B9 Ch 3 EXT GND B15 Ch 4 EXT SIN HI B14 Ch 4 EXT COS HI B13 C...

Page 37: ...75DS2 Connector Pin Out Information 75DS2 Operations Manual North Atlantic Industries Inc 11 11 2011 Rev 2011 11 11 1000 www naii com Page 37 of 43 Dimensions ...

Page 38: ...2V DC POWER OPTION Note 1 0 cPCI Power is used 1 cPCI 12VDC Power is isolated from PCB power planes User to connect external power via J4 Front Panel connector See Pin out tables CODE Reserved for special configurations leave open for standard Note 1 12 VDC Power Option Additional or alternate 12V power pins are available that may be specified at time of order See part number The additional power ...

Page 39: ...of 43 Note 4 Remote sensing is provided for each channel to eliminate errors caused by voltage drops on the interconnecting cables The user must connect the load sense connections i e Ch 3 Sense S1 to the respective output signals Connecting at the load is desirable to mitigate accuracy errors dependent on line and load resistance ...

Page 40: ... 1 5 Programmable SYN or RSL 18 SYN RSL 2 28 2 115 47 440 1 5 Channel 1 SYN Channel 2 RSL 19 RSL SYN 2 28 2 115 47 440 1 5 Channel 1 RSL Channel 2 SYN 1A RSL 2 28 2 115 1K 3K 1 5 1B RSL 2 28 2 115 3K 5K 1 5 1C RSL 2 28 2 115 5K 7K 1 5 1D RSL 2 28 2 115 7K 10K 1 5 1E SYN 2 11 8 2 115 400 1K 1 5 1F SYN 2 11 8 2 115 47 400 1 5 1G SYN 2 11 8 2 115 1K 3K 1 5 1H SYN 2 11 8 2 115 3K 5K 1 5 1J SYN 2 11 8 ...

Page 41: ... 1K 3 0 31 RSL 2 28 2 115 400 1K 3 0 35 SYN 11 8 2 115 47 440 3 0 36 RSL 2 28 2 115 47 440 3 0 3A RSL 2 28 2 115 1K 3K 3 0 3B RSL 2 28 2 115 3K 5K 3 0 3C RSL 2 28 2 115 5K 7K 3 0 3D RSL 2 28 2 115 7K 10K 3 0 3E SYN 2 11 8 2 115 1K 3K 3 0 3F SYN 2 11 8 2 115 3K 5K 3 0 3G SYN 2 11 8 2 115 5K 7K 3 0 3H SYN 2 11 8 2 115 7K 10K 3 0 3J SYN 2 28 2 115 1K 3K 3 0 3K SYN 2 28 2 115 3K 5K 3 0 3L SYN 2 28 2 1...

Page 42: ...x Load VA 50 DLV 2 28 2 115 360 1 1K 1 5 51 DLV 2 28 2 115 47 440 1 5 52 DLV 2 28 2 115 1K 3K 1 5 53 DLV 2 28 2 115 3K 5K 1 5 54 DLV 2 28 2 115 5K 7K 1 5 55 DLV 2 28 2 115 7K 10K 1 5 50 DLV 2 28 2 115 360 1 1K 1 5 51 DLV 2 28 2 115 47 440 1 5 52 DLV 2 28 2 115 1K 3K 1 5 53 DLV 2 28 2 115 3K 5K 1 5 54 DLV 2 28 2 115 5K 7K 1 5 55 DLV 2 28 2 115 7K 10K 1 5 1 There is a 10 tolerance on the upper limit...

Page 43: ... products or services mentioned in this document are held by the companies producing them Revision Description of Change Engineer Date 2011 11 11 1000 1 G4 Description sub doc updated clarified to reference 6 possible range s 2 D S 2CHI Specification sub doc corrected minor typo KHz 3 K9 Specification sub doc output characteristics clarified external VCC source required for high side and push pull...

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