North Atlantic 75DS2 Operation Manual Download Page 24

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DLV Two/Four Channel (Module 5*)

75DS2 Operations Manual

North Atlantic Industries, Inc.

11/11/2011

Rev: 2011-11-11-1000

www.naii.com

Page 24 of 43

DLV BIT Test Enable

Set bit to enable associated Built-In Self Test D2 or D3.

The on-line (D2) Test -

Writing “1” to the D2 bit of the

DLV Test Enable Register

initiates status reporting of the

automatic background BIT testing that checks the output accuracy of each channel by comparing the measured
output position to the commanded position. The status bits will be set to indicate an accuracy (0.05º) problem and
the results can be read from DLV Status Registers within 2 seconds and if enabled, an interrupt will be generated
(See Interrupt Register). Writing a “0” deactivates the status reporting. The testing is totally transparent to the
user, requires no external programming, and has no effect on the standard operation of this card.

Note:

Outputs

must be ON and Excitation supplied for test to function. Card will write 55h (every 0.1 seconds) to the DLV Test
(D2) Verify Register when D2 is enabled. User can periodically clear to 00h and then read the

DLV Test (D2)

Verify Register

again, after 0.1 seconds, to verify that BIT Testing is activated. This test continuously sequences

between the channels on the card with each output being measured for approximately 180mSec. If the measured
position has an error greater the 0.05º, a flag will be set in the appropriate register. If the input position is stepped
more than 0.05º during a test cycle, the test cycle will not generally indicate an error.

In addition, each DLV Excitation input and signal output is continually monitored. Any failure triggers an Interrupt
(if enabled) and the results are available in the

DLV Signal

and

DLV Excitation Status Registers.

The off-line (D3) Test -

Writing “1” to the D3 bit of the

DLV Test Enable Register

initiates a BIT Test that

generates and tests 72 different positions to an accuracy of 0.05



. External excitation is required and outputs

must be ON. The DLV Status bits will be set to indicate an accuracy problem. Results are available in the

DLV

Test Status Registers

and if enabled, an interrupt will be generated (See

Interrupt Register

). Test cycle takes

about 30 seconds and the D3 bit changes from “1” to “0” when test is complete. The testing requires no external
programming,

and can be terminated at any time by writing a “0” to the D3 bit of the

DLV Test Enable Register.

CAUTION:

Outputs must be ON and Excitation must be supplied during this test. Output is therefore

active. Check connected loads for possible interaction.

D15

D14

D13

D12

D11

D10

Test Enable

Test (D2) Verify

Card will write 55h at

Test (D2) Verification

can clear to 00h and then read again, after approximately one second, to verify that background bit testing is
activated.

DLV Output Mode

The DLV Output Mode register is utilized for selecting either ratio-metric or absolute (fixed) mode voltages. Ratio-
metric Mode, when selected, will cause the output signal voltage of the channel to vary with the input Excitation.
Fixed Mode, when selected, will set the output to a required magnitude that will not vary with excitation input and
set in the DLV Signal Voltage register regardless of the actual input excitation voltage applied. Set register to “0”
for Ratio-

metric Mode. Set register to “1” for Fixed Mode.

DLV 2-Wire or 3/4-Wire Select

Where a

pplicable, write an “01” or “10” (4-Wire = 01; 2-Wire = 10) to each corresponding channel bit pair,

representing a channel commanded output format, of the

DLV 2-Wire or 3/4 Wire Select Register.

D15

D14

D13

D12

D11

D10