CHAPTER 3 CPU ARCHITECTURE
User's Manual U11919EJ3V0UM00
55
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Stack pointer (SP)
This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed
RAM area can be set as the stack area.
Figure 3-13. Stack Pointer Configuration
The SP is decremented ahead of write (save) to the stack memory and is incremented after read (restore)
from the stack memory.
Each stack operation saves/restores data as shown in Figures 3-14 and 3-15.
Caution
Since RESET input makes SP contents undefined, be sure to initialize the SP before
instruction execution.
Figure 3-14. Data to be Saved to Stack Memory
Figure 3-15. Data to be Restored from Stack Memory
0
15
SP14
SP15
SP
SP13 SP12 SP11 SP10
SP9
SP8
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
Interrupt
PSW
PC15 to PC8
PC15 to PC8
PC7 to PC0
Lower Half
Register Pairs
SP SP _ 2
SP _ 2
CALL, CALLT
Instructions
PUSH rp
Instruction
SP _ 1
SP
SP SP _ 2
SP _ 2
SP _ 1
SP
PC7 to PC0
SP _ 3
SP _ 2
SP _ 1
SP
SP SP _ 3
Upper Half
Register Pairs
RETI Instruction
PSW
PC15 to PC8
PC15 to PC8
PC7 to PC0
Lower Half
Register Pairs
RET Instruction
POP rp
Instruction
SP
PC7 to PC0
Upper Half
Register Pairs
SP + 1
SP SP + 2
SP
SP + 1
SP SP + 2
SP
SP + 1
SP + 2
SP SP + 3
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Summary of Contents for UPD789026 Series
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