NEC UPD789026 Series, User Manual

Page: 90 / 213

CHAPTER 5 CLOCK GENERATION CIRCUIT
User's Manual U11919EJ3V0UM00
90
5.5 Operation of Clock Generation Circuit
The clock generation circuit generates the following clocks and controls operation modes of the CPU, such as
the standby mode:
•
System clock f
X
•
CPU clock f
CPU
•
Clock to peripheral hardware
The operation of the clock generation circuit is determined by the processor clock control register (PCC), as
follows:
(a) The slow mode 2 f
CPU
(1.6
µ
s: at 5.0-MHz operation) of the system clock is selected when the RESET signal
is generated (PCC = 02H). While a low level is input to the RESET pin, oscillation of the system clock is
stopped .
(b) Two types of CPU clocks f
CPU
(0.2
µ
s and 0.8
µ
s: at 5.0-MHz operation) can be selected by the PCC
setting.
(c) Two standby modes, STOP and HALT, can be used.
(d) The clock to the peripheral hardware is supplied by dividing the system clock. The other peripheral
hardware is stopped when the system clock is stopped (except, however, the external clock input
operation).
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