NEC UPD789026 Series, User Manual

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User's Manual U11919EJ3V0UM00
17
LIST OF FIGURES (1/3)
Figure No. Title Page
2-1 List of Pin Input/Output Circuits................................................................................................................. 40
3-1 Memory Map (
µ
PD789022) ....................................................................................................................... 41
3-2 Memory Map (
µ
PD789024) ....................................................................................................................... 42
3-3 Memory Map (
µ
PD789025) ....................................................................................................................... 43
3-4 Memory Map (
µ
PD789026) ....................................................................................................................... 44
3-5 Memory Map (
µ
PD78F9026A) .................................................................................................................. 45
3-6 Data Memory Addressing (
µ
PD789022) ................................................................................................... 48
3-7 Data Memory Addressing (
µ
PD789024) ................................................................................................... 49
3-8 Data Memory Addressing (
µ
PD789025) ................................................................................................... 50
3-9 Data Memory Addressing (
µ
PD789026) ................................................................................................... 51
3-10 Data Memory Addressing (
µ
PD78F9026A)............................................................................................... 52
3-11 Program Counter Configuration ................................................................................................................ 53
3-12 Program Status Word Configuration ......................................................................................................... 53
3-13 Stack Pointer Configuration ...................................................................................................................... 55
3-14 Data to be Saved to Stack Memory .......................................................................................................... 55
3-15 Data to be Restored from Stack Memory .................................................................................................. 55
3-16 General-Purpose Register Configuration .................................................................................................. 56
4-1 Port Types................................................................................................................................................. 69
4-2 Block Diagram of P00 to P07 .................................................................................................................... 71
4-3 Block Diagram of P10 to P17 .................................................................................................................... 72
4-4 Block Diagram of P20 ............................................................................................................................... 73
4-5 Block Diagram of P21 ............................................................................................................................... 74
4-6 Block Diagram of P22 ............................................................................................................................... 75
4-7 Block Diagram of P30 to P32 .................................................................................................................... 76
4-8 Block Diagram of P40 to P47 .................................................................................................................... 77
4-9 Block Diagram of P50 ............................................................................................................................... 78
4-10 Block Diagram of P51 ............................................................................................................................... 79
4-11 Block Diagram of P52 and P53 ................................................................................................................. 80
4-12 Port Mode Register Format ....................................................................................................................... 82
4-13 Pull-Up Resistor Option Register Format .................................................................................................. 82
5-1 Block Diagram of Clock Generation Circuit ............................................................................................... 85
5-2 Processor Clock Control Register Format................................................................................................. 86
5-3 External Circuit of System Clock Oscillation Circuit .................................................................................. 87
5-4 Incorrect Examples of Resonator Connection........................................................................................... 88
5-5 Switching CPU Clock ................................................................................................................................ 91
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