µ
PD754144, 754244
10
Data Sheet U10040EJ2V1DS
3.2 Non-port Pins
Pin Name
Input/Output
Alternate
Function
After Reset
I/O Circuit
Function
TYPE
Note
PTO0
Output
P30
Timer counter output pins
Input
E-B
PTO1
P31
PTO2
P32
INT0
Input
P61
Edge detection vectored
Noise elimination
Input
F -A
interrupt input pin
circuit can be
(detected edge can be
selected.
selected)
Asynchronous
Noise elimination circuit
input
can be selected.
KR4 to KR7
Input
P70 to P73
Falling edge detection testable input pins
Input
B -A
PTH00
Input
P62
Threshold voltage-variable 2-bit analog input pins
Input
F -A
PTH01
P63
KRREN
Input
–
Key return reset enable pin
Input
B
The reset signal is generated at the falling edge
of KRn while KRREN is high in STOP mode.
AV
REF
Input
P60
Reference voltage input pin
Input
F -A
CL1
–
–
Incorporated in the
µ
PD754144 only
–
–
RC (for system clock oscillation) connection pin
CL2
–
External clock cannot be input.
X1
Input
–
Incorporated in the
µ
PD754244 only
–
–
Crystal/ceramic resonator (for system clock
oscillation) connection pin
X2
–
When inputting the external clock, input the external
clock to pin X1 and input the inverted phase of the
external clock to pin X2.
RESET
Input
–
System reset input pin (low-level active)
–
B -A
Pull-up resistor can be incorporated (mask option).
IC
–
–
Internally Connected Connect directly to V
DD
.
–
–
V
DD
–
–
Positive supply pin
–
–
V
SS
–
–
Ground potential
–
–
Note
Circled characters indicate the Schmitt-trigger input.
*
