NEC Mu754244 Datasheet Download Page 13

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PD754144, 754244

Data Sheet U10040EJ2V1DS

4. SWITCHING FUNCTION BETWEEN MK I MODE AND MK II MODE

4.1 Difference between Mk I and Mk II Modes

The

PD754244 75XL CPU has the following two modes: Mk I and Mk II, either of which can be selected. The

mode can be switched by the bit 3 of the Stack Bank Select register (SBS).

• Mk I mode:

Instructions are compatible with the 75X series. Can be used in the 75XL CPU with a ROM

capacity of up to 16 Kbytes.

• Mk II mode:

Incompatible with 75X series. Can be used in all the 75XL CPU’s including those products

whose ROM capacity is more than 16 Kbytes.

Table 4-1. Differences between Mk I Mode and Mk II Mode

Mk I Mode

Mk II Mode

Number of stack bytes

2 bytes

3 bytes

for subroutine instructions

BRA !addr1 instruction

Not available

Available

CALLA !addr1 instruction

CALL !addr instruction

3 machine cycles

4 machine cycles

CALLF !faddr instruction

2 machine cycles

3 machine cycles

Caution The Mk II mode supports a program area exceeding 16 Kbytes for the 75X and 75XL Series.

Therefore, this mode is effective for enhancing software compatibility with products that

have a program area of more than 16 Kbytes.

With regard to the number of stack bytes during execution of subroutine call instructions,

the usable area increases by 1 byte per stack compared to the Mk I mode when the Mk II

mode is selected.

However, when the CALL !addr and CALLF !faddr instructions are used, the machine cycle

becomes longer by 1 machine cycle. Therefore, if more emphasis is placed on RAM use

efficiency and processing performance than on software compatibility, the Mk I mode

should be used.

Summary of Contents for Mu754244

Page 1: ...ry static RAM 128 4 bits Instruction execution time variable function suited for power saving µPD754144 4 8 16 64 µs at fcc 1 0 MHz operation µPD754244 0 95 1 91 3 81 15 3 µs at fx 4 19 MHz operation 0 67 1 33 2 67 10 7 µs at fx 6 0 MHz operation APPLICATIONS Automotive appliances such as key less entry compact data carrier etc Unless contextually excluded references in this data sheet to the µPD7...

Page 2: ...0 mil 0 65 mm pitch µPD754144GS xxx GJG A 20 pin plastic shrink SOP 300 mil 0 65 mm pitch µPD754244GS xxx BA5 20 pin plastic SOP 300 mil 1 27 mm pitch µPD754244GS xxx BA5 A 20 pin plastic SOP 300 mil 1 27 mm pitch µPD754244GS xxx GJG 20 pin plastic shrink SOP 300 mil 0 65 mm pitch µPD754244GS xxx GJG A 20 pin plastic shrink SOP 300 mil 0 65 mm pitch Remarks 1 Products with A at the end of the part...

Page 3: ...or can be specified by mask option port CMOS input output 9 On chip pull up resistor connection can be specified by means of software Total 13 Start up time after reset 56 fcc 2 17 fx 2 15 fx selected by mask option Stand by mode release time 29 fcc 220 fx 217 fx 215 fx 213 fx selected by the setting of BTM Timer 4 channels 8 bit timer counter can be used as 16 bit timer counter 3 channels Basic i...

Page 4: ...18 7 PERIPHERAL HARDWARE FUNCTIONS 19 7 1 Digital Input Output Ports 19 7 2 Clock Generator 19 7 3 Basic Interval Timer Watchdog Timer 22 7 4 Timer Counter 23 7 5 Programmable Threshold Port Analog Input Port 27 7 6 Bit Sequential Buffer 16 Bits 28 8 INTERRUPT FUNCTION AND TEST FUNCTION 29 9 STANDBY FUNCTION 31 10 RESET FUNCTION 32 10 1 Configuration and Operation Status of RESET Function 32 10 2 ...

Page 5: ...TION FREQUENCY CHARACTERISTICS EXAMPLES REFERENCE VALUES 72 16 PACKAGE DRAWINGS 76 17 RECOMMENDED SOLDERING CONDITIONS 78 APPENDIX A COMPARISON OF FUNCTIONS AMONG µPD754144 754244 AND 75F4264 81 APPENDIX B DEVELOPMENT TOOLS 82 APPENDIX C RELATED DOCUMENTS 85 ...

Page 6: ...A5 µPD754144GS BA5 A 20 pin Plastic Shrink SOP 300 mil 0 65 mm pitch µPD754144GS GJG µPD754144GS GJG A IC Internally Connected Connect to VDD directly 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 RESET CL1 CL2 VSS IC VDD P60 AVREF P61 INT0 P62 PTH00 P63 PTH01 KRREN P80 P30 PTO0 P31 PTO1 P32 PTO2 P33 P70 KR4 P71 KR5 P72 KR6 P73 KR7 ...

Page 7: ...0 Port 8 IC Internally connected PTH00 and PTH01 Programmable threshold port analog inputs 0 and 1 INT0 External vectored interrupt 0 PTO0 to PTO2 Programmable timer outputs 0 to 2 KR4 to KR7 Key returns 4 to 7 RESET Reset KRREN Key return reset enable VDD Positive power supply P30 to P33 Port 3 VSS Ground P60 to P63 Port 6 X1 and X2 System clock crystal ceramic 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16...

Page 8: ...T2 PTO0 P30 PTO1 P31 PTO2 P32 INT0 P61 KRREN KR4 P70 to KR7 P73 AVREF P60 PTH00 P62 PTH01 P63 ALU PROGRAM COUNTER PROGRAM MEMORY ROM 4096 8 BITS DECODE AND CONTROL CY SP 8 SBS BANK GENERAL REG DATA MEMORY RAM 128 4 BITS EEPROM 16 8 BITS PORT3 4 PORT6 4 PORT7 4 PORT8 BIT SEQ BUFFER 16 P30 to P33 P60 to P63 P70 to P73 P80 CLOCK DIVIDER SYSTEM CLOCK GENERATOR STAND BY CONTROL fX 2N CL1 CL2 X1 X2 φ CP...

Page 9: ...on chip pull up resistor connection when using the programmable threshold port Programmable 4 bit input output port PORT3 This port can be specified input output bit wise On chip pull up resistor connection can be specified by software in 4 bit units Programmable 4 bit input output port PORT6 This port can be specified input output bit wise On chip pull up resistor can be specified by software in ...

Page 10: ...y return reset enable pin Input B The reset signal is generated at the falling edge of KRn while KRREN is high in STOP mode AVREF Input P60 Reference voltage input pin Input F A CL1 Incorporated in the µPD754144 only RC for system clock oscillation connection pin CL2 External clock cannot be input X1 Input Incorporated in the µPD754244 only Crystal ceramic resonator for system clock oscillation co...

Page 11: ...le N ch P ch IN OUT VDD P ch output disable data P U R enable Type D Type A IN OUT VDD P U R Mask Option IN VDD P U R P U R enable P ch IN OUT Type D Type B output disable data P U R Pull Up Resistor P U R Pull Up Resistor P U R Pull Up Resistor Schmitt trigger input having hysteresis characteristic CMOS specification input buffer Push pull output that can be placed in output high impedance both P...

Page 12: ... P32 PTO2 P33 P60 AVREF P61 INT0 P62 PTH00 P63 PTH01 P70 KR4 Connect to VDD P71 KR5 P72 KR6 P73 KR7 P80 Input state Independently connect to VSS or VDD via a resistor Output state Leave open KRREN When this pin is connected to VDD internal reset signal is gener ated at the falling edge of the KRn pin in the STOP mode When this pin is connected to VSS internal reset signal is not generated even if ...

Page 13: ...s for subroutine instructions BRA addr1 instruction Not available Available CALLA addr1 instruction CALL addr instruction 3 machine cycles 4 machine cycles CALLF faddr instruction 2 machine cycles 3 machine cycles Caution The Mk II mode supports a program area exceeding 16 Kbytes for the 75X and 75XL Series Therefore this mode is effective for enhancing software compatibility with products that ha...

Page 14: ...ng of a program When using the Mk II mode it must be initialized to 0000B Figure 4 1 Stack Bank Select Register Format Caution Because SBS 3 is set to 1 after a RESET signal is generated the CPU operates in the Mk I mode When executing an instruction in the Mk II mode set SBS 3 to 0 to select the Mk II mode Address Stack area specification Symbol SBS F84H SBS3 SBS2 SBS1 SBS0 3 2 1 0 Memory bank 0 ...

Page 15: ...gram start address and values set for the RBE and MBE by the vectored interrupts are written Interrupt service can be started at an arbitrary address Addresses 0020H to 007FH Table area referenced by the GETI instructionNote Note The GETI instruction realizes a 1 byte instruction on behalf of an arbitrary 2 byte instruction 3 byte instruction or two 1 byte instructions It is used to decrease the p...

Page 16: ...0 start address low order 8 bits MBE RBE INTT0 start address high order 4 bits INTT0 start address low order 8 bits MBE RBE INTT1 INTT2 start address high order 4 bits INTT1 INTT2 start address low order 8 bits MBE RBE 0 0 0 0 0 0 0 0 0 0 0 0 INTEE start address high order 4 bits INTEE start address low order 8 bits GET instruction reference table 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H 00...

Page 17: ...Map 000H 01FH 020H 07FH 080H 0FFH 400H 41FH 420H 4FFH F80H FFFH 128 4 Not incorporated 16 8 Not incorporated 128 4 96 4 32 4 0 4 15 General purpose register area Stack area Data area static RAM 128 4 Data area EEPROM 16 8 Peripheral hardware area Data memory Memory bank ...

Page 18: ...ipulation auto erase auto write is available by memory manipulation instruction as well as for static RAM However available instructions are restricted 3 It can reduce loads of software because the auto erase and or auto write operation is performed by hardware 4 Write operation control using the interrupt request The interrupt request is generated under following conditions Terminates write opera...

Page 19: ...nly port Also used as KR4 to KR7 pins On chip pull up resistor connection can be specified by mask option bit wise PORT8 1 bit I O Can be set to input or output mode bit wise _ 7 2 Clock Generator The clock generator provides the clock signals to the CPU and peripheral hardware Its configuration is shown in Figures 7 1 and 7 2 The operation of the clock generator is set with the processor clock co...

Page 20: ...the CPU clock is equal to one machine cycle of the instruction CL1 CL2 System clock oscillator Oscillation stops 1 1 1 4096 1 2 1 4 1 16 fcc Divider 1 4 Φ HALT F F S R Q S R Q STOP F F PCC0 PCC1 PCC2 PCC3 PCC2 PCC3 clear HALTNote STOPNote Wait release signal from BT Reset signal Standby release signal from interrupt control circuit PCC 4 Basic interval timer BT Timer counter INT0 noise eliminator ...

Page 21: ...tCY of the CPU clock is equal to one machine cycle of the instruction X1 X2 System clock oscillator Oscillation stops 1 2 1 4 1 16 fX Divider 1 4 Φ HALT F F S R Q S R Q STOP F F PCC0 PCC1 PCC2 PCC3 PCC2 PCC3 clear HALTNote STOPNote Wait release signal from BT Reset signal Standby release signal from interrupt control circuit PCC 4 Basic interval timer BT Timer counter INT0 noise eliminator 1 1 1 4...

Page 22: ... the wait time cannot be specified when the standby mode is released The oscillation stabilization wait time is negligible in the µPD754144 and this device returns to the normal operation mode after counting 29 fCC 512 µs fCC 1 0 MHz operation In the µPD754244 crystal ceramic oscillation on the other hand the wait time can be specified when the standby mode is released 2 Instruction execution From...

Page 23: ...terval timer operation b Square wave output of any frequency to PTO0 PTO2 pins c Count value read function The timer counter can operate in the following four modes as set by the mode register Table 7 2 Mode List Mode Channel Channel 0 Channel 1 Channel 2 TM11 TM10 TM21 TM20 8 bit timer counter mode 0 0 0 0 PWM pulse generator mode 0 0 0 1 16 bit timer counter mode 1 0 1 0 Carrier generator mode 0...

Page 24: ...1 to 0 TM06 fx 24 fx 26 fx 28 fx 210 TM05 TM04 TM03 TM02 0 0 TM0 Match SET1Note 8 8 8 MPX From clock generator Timer operation start CP Clear Count register 8 T0 8 8 Comparator 8 Modulo register 8 TMOD0 TOUT F F Reset TOE0 PORT3 0 PMGA bit 0 T0 enable flag P30 Output latch Port 3 input output mode Output buffer P30 PTO0 INTT0 IRQT0 set signal RESET IRQT0 clear signal Internal bus ...

Page 25: ...de Selector Match Reset TOUT F F TOE1 PORT3 1 PMGA bit 1 T1 enable flag P31 Output latch Port 3 input output mode Output buffer P31 PTO1 INTT1 IRQT1 set signal RESET IRQT1 clear signal Timer counter channel 2 match signal When 16 bit timer counter mode Timer counter channel 2 comparator When 16 bit timer counter mode Timer counter channel 2 reload signal Internal bus fx 25 fx 26 fx 28 fx 210 fx 21...

Page 26: ... F T2 High level period setting modulo register 8 Modulo register 8 Reset TOE2 REMC NRZB NRZ 0 8 TMOD2 TMODH TC2 Reload Overflow Carrier generator mode PORT3 2 PMGA bit 2 Output latch Port 3 input output mode Output buffer P32 PTO2 Timer counter channel 1 clock input INTT2 IRQT2 set signal RESET IRQT2 clear signal Timer counter channel 1 match signal When 16 bit timer counter mode Timer counter ch...

Page 27: ... input pins 1 Comparator operation 2 4 bit resolution A D converter operation controlled by software Caution Do not specify an on chip pull up resistor connection for Port 6 when using the programmable threshold port Figure 7 7 Programmable Threshold Port Block Diagram PTH00 PTH01 AVREF 1 2 R R R 1 2 R MPX VREF PTHM7 PTHM PTHM6 PTHM5 PTHM4 PTHM3 PTHM2 PTHM1 PTHM0 8 Operate stop Standby mode signal...

Page 28: ...fication in sequence therefore it is useful when processing large data bit wise Figure 7 8 Bit Sequential Buffer Format Remarks 1 In the pmem L addressing the specified bit moves corresponding to the L register 2 In the pmem L addressing the BSB can be manipulated regardless of MBE MSB specification Address Bit Symbol L register L FH L CH L BH L 8H L 7H L 4H L 3H L 0H DECS L INCS L BSB3 BSB2 BSB1 ...

Page 29: ...ent by the interrupt enable flag IE and interrupt master enable flag IME Can set any interrupt start address Multiple interrupts wherein the order of priority can be specified by the interrupt priority select register IPS Test function of interrupt request flag IRQ An interrupt generated can be checked by software Release the standby mode A release interrupt can be selected by the interrupt enable...

Page 30: ...rupt request flag IRQ2 is set at the KRn pin falling edge when IM20 1 and IM21 0 Internal bus Interrupt enable flag IE 2 4 IM2 IM0 Note1 Edge detector INT0 P61 INTBT INTT0 INTT1 INTT2 INTEE IRQBT IRQ0 IRQT0 IRQT1 IRQT2 IRQEE IRQ2 KR4 P70 KR7 P73 Falling edge detectorNote2 Key return reset circuit IM2 IME IPS IST1 IST0 Decoder VRQn Priority control ciricuit Standby release signal Selector Vector ta...

Page 31: ...ion stops Operable watchdog timer BT mode The IRQBT is set in the basic time interval WT mode Reset is generated by the BT overflow Timer Operation stops Operable External interrupt INT0 is not operable Note INT2 is operable during KRn falling period only CPU The operation stops Release signal Reset signal Reset signal Interrupt request signal sent from Interrupt request signal sent from interrupt...

Page 32: ... by a falling edge signal from KRn in the STOP mode When any of these reset signals is input an internal reset signal is generated The configuration is shown in Figure 10 1 Figure 10 1 Configuration of Reset Function VDD Mask option Output buffer KRREN RESET Q R S Q S R Q S R Instruction Interrupt STOP mode KRF WDF Watchdog timer overflow Internal reset signal Instruction One shot pulse generator ...

Page 33: ...Generation Note In the µPD754144 the wait time is fixed to 56 fcc 56µs 1 0 MHz operation In the µPD754244 the wait time can be selected from the following two time settings by means of the mask option 217 fx 21 8 ms 6 0 MHz operation 31 3 ms 4 19 MHz operation 215 fx 5 46 ms 6 0 MHz operation 7 81 ms 4 19 MHz operation Operation mode or standby mode WaitNote RESET signal generated Operation mode H...

Page 34: ...Held Undefined Data memory EEPROM HeldNote 1 HeldNote 2 EEPROM write control register EWC 0 0 General purpose register X A H L D E B C Held Undefined Bank select register MBS RBS 0 0 0 0 Basic interval Counter BT Undefined Undefined timer watchdog Mode register BTM 0 0 timer Watchdog timer enable flag WDTM 0 0 Timer counter Counter T0 0 0 channel 0 Modulo register TMOD0 FFH FFH Mode register TM0 0...

Page 35: ...priority selection register IPS 0 0 INT0 2 mode registers IM0 IM2 0 0 0 0 Digital port Output buffer Off Off Output latch Cleared 0 Cleared 0 I O mode registers PMGA C 0 0 Pull up resistor setting register POGA B 0 0 Bit sequential buffer BSB0 BSB3 Held Undefined Table 10 1 Hardware Status After Reset 3 3 RESET signal RESET signal RESET signal RESET signal Hardware generation by key generation in ...

Page 36: ...ding to each signal Figure 10 3 shows the WDF operation in generating each signal and Figure 10 4 shows the KRF operation in generating each signal Table 10 2 WDF and KRF Contents Correspond to Each Signal External RESET Reset signal Reset signal WDF clear KRF clear Hardware signal generation generation by watch generation by the instruction instruction dog timer overflow KRn input execution execu...

Page 37: ...peration mode Internal reset operation STOP mode Internal reset operation Internal reset operation HALT mode Operation mode STOP mode HALT mode Operation mode STOP instruction execution Reset signal generation by the KRn input External RESET signal generation STOP instruction execution KRF clear instruction execution Reset signal generation by the KRn input ...

Page 38: ... pin On chip pull up resistor connection can be specified for this pin 1 Do not connect an on chip pull up resistor 2 Connect the 100 kΩ typ pull up resistor Standby function mask option µPD754244 only Note The wait time when the RESET signal is input can be selected 1 217 fX 21 8 ms fX 6 0 MHz operation 31 3 ms fX 4 19 MHz operation 2 215 fX 5 46 ms fX 6 0 MHz operation 7 81 ms fX 4 19 MHz operat...

Page 39: ... in the labels that can be described for fmem and pmem For details refer to µPD754144 754244 user s manual U10676E Expression Description method format reg X A B C D E H L reg1 X B C D E H L rp XA BC DE HL rp1 BC DE HL rp2 BC DE rp XA BC DE HL XA BC DE HL rp 1 BC DE HL XA BC DE HL rpa HL HL HL DE DL rpa1 DE DL n4 4 bit immediate data or label n8 8 bit immediate data or label mem 8 bit immediate da...

Page 40: ...xtended register pair DE DE extended register pair HL HL extended register pair PC Program counter SP Stack pointer CY Carry flag bit accumulator PSW Program status word MBE Memory bank enable flag RBE Register bank enable flag PORTn Port n n 3 6 7 8 IME Interrupt master enable flag IPS Interrupt priority selection register IE Interrupt enable flag RBS Register bank selection register MBS Memory b...

Page 41: ...emory bank that can be accessed 2 In 2 MB 0 independently of how MBE and MBS are set 3 In 4 and 5 MB 15 independently of how MBE and MBS are set 4 6 to 11 indicate the areas that can be addressed 4 Explanation of number of machine cycles column S denotes the number of machine cycles required by skip operation when a skip instruction is executed The value of S varies as follows When no skip is made...

Page 42: ...L FH A rpa1 1 1 A rpa1 2 XA HL 2 2 XA HL 1 HL A 1 1 HL A 1 HL XA 2 2 HL XA 1 A mem 2 2 A mem 3 XA mem 2 2 XA mem 3 mem A 2 2 mem A 3 mem XA 2 2 mem XA 3 A reg 2 2 A reg XA rp 2 2 XA rp reg1 A 2 2 reg1 A rp 1 XA 2 2 rp 1 XA XCH A HL 1 1 A HL 1 A HL 1 2 S A HL then L L 1 1 L 0 A HL 1 2 S A HL then L L 1 1 L FH A rpa1 1 1 A rpa1 2 XA HL 2 2 XA HL 1 A mem 2 2 A mem 3 XA mem 2 2 XA mem 3 A reg1 1 1 A r...

Page 43: ...A HL 1 1 S A A HL 1 carry XA rp 2 2 S XA XA rp carry rp 1 XA 2 2 S rp 1 rp 1 XA carry ADDC A HL 1 1 A CY A HL CY 1 XA rp 2 2 XA CY XA rp CY rp 1 XA 2 2 rp 1 CY rp 1 XA CY SUBS A HL 1 1 S A A HL 1 borrow XA rp 2 2 S XA XA rp borrow rp 1 XA 2 2 S rp 1 rp 1 XA borrow SUBC A HL 1 1 A CY A HL CY 1 XA rp 2 2 XA CY XA rp CY rp 1 XA 2 2 rp 1 CY rp 1 XA CY AND A n4 2 2 A A n4 A HL 1 1 A A HL 1 XA rp 2 2 XA...

Page 44: ...ag SET1 CY 1 1 CY 1 manipulation instruction CLR1 CY 1 1 CY 0 SKT CY 1 1 S Skip if CY 1 CY 1 NOT1 CY 1 1 CY CY Memory bit SET1 mem bit 2 2 mem bit 1 3 manipulation instructions fmem bit 2 2 fmem bit 1 4 pmem L 2 2 pmem7 2 L3 2 bit L1 0 1 5 H mem bit 2 2 H mem3 0 bit 1 1 CLR1 mem bit 2 2 mem bit 0 3 fmem bit 2 2 fmem bit 0 4 pmem L 2 2 pmem7 2 L3 2 bit L1 0 0 5 H mem bit 2 2 1 SKT mem bit 2 2 S Ski...

Page 45: ... 2 CY CY H mem3 0 bit 1 XOR1 CY fmem bit 2 2 CY CY v fmem bit 4 CY pmem L 2 2 CY CY v pmem7 2 L3 2 bit L1 0 5 CY H mem bit 2 2 CY CY v H mem3 0 bit 1 Branch BRNote 1 addr PC11 0 addr 6 instructions Select appropriate instruction among BR addr BRCB caddr and BR addr according to the assembler being used addr1 PC11 0 addr 11 Select appropriate instruction among BR addr BRA addr1 BRCB caddr and BR ad...

Page 46: ...6 SP 3 SP 4 PC11 0 SP 5 0 0 0 0 PC11 0 0 faddr SP SP 6 RETNote 1 3 PC11 0 SP SP 3 SP 2 MBE RBE 0 0 SP 1 SP SP 4 MBE RBE SP 4 0 0 0 0 SP 1 PC11 0 SP SP 3 SP 2 SP SP 6 RETSNote 1 3 S MBE RBE 0 0 SP 1 Unconditional PC11 0 SP SP 3 SP 2 SP SP 4 then skip unconditionally 0 0 0 0 SP 1 PC11 0 SP SP 3 SP 2 MBE RBE SP 4 SP SP 6 then skip unconditionally RETINote 1 3 MBE RBE 0 0 SP 1 PC11 0 SP SP 3 SP 2 PSW ...

Page 47: ... RBE 0 0 PC11 0 taddr 3 0 taddr 1 SP SP 4 When instruction other than TBR and Depending on TCALL instructions the reference taddr taddr 1 instruction is executed instruction 3 When TBR instruction 10 PC11 0 taddr 3 0 taddr 1 4 When TCALL instruction SP 6 SP 3 SP 4 PC11 0 SP 5 0 0 0 0 SP 2 MBE RBE PC11 0 taddr 3 0 taddr 1 SP SP 6 3 When instruction other than TBR and Depending on TCALL instructions...

Page 48: ...nt low IOL Per pin 20 mA For all pins 90 mA Operating ambient TA 40 to 85 C temperature Storage temperature Tstg 65 to 150 C Caution If any of the parameters exceeds the absolute maximum ratings even momentarily the quality of the product may be impaired The absolute maximum ratings are values that may physically damage the products Be sure to use the products within the ratings Capacitance TA 25 ...

Page 49: ...aracteristics Caution When using the oscillation circuit of the system clock wire the portion enclosed in dotted lines in the figures as follows to avoid adverse influences on the wiring capacitance Keep the wire length as short as possible Do not cross other signal lines Do not route the wiring in the vicinity of lines though which a high fluctuating current flows Always keep the ground point of ...

Page 50: ...w level input VIL1 Port 3 2 7 V VDD 6 0 V 0 0 3VDD V voltage 1 8 V VDD 2 7 V 0 0 1VDD V VIL2 Ports 6 to 8 2 7 V VDD 6 0 V 0 0 2VDD V KRREN RESET 1 8 V VDD 2 7 V 0 0 1VDD V High level VOH VDD 4 5 to 6 0 V IOH 1 0 mA VDD 1 0 V output voltage VDD 1 8 to 6 0 V IOH 100 µA VDD 0 5 V Low level VOL VDD 4 5 to 6 0 V Port 3 IOL 15 mA 0 6 2 0 V output voltage Ports 6 8 0 4 V IOL 1 6 mA VDD 1 8 to 6 0 V IOH 4...

Page 51: ... oscillation VDD 3 0 V 10 Note 3 0 55 1 6 mA IDD2 R 5 1 kΩ HALT VDD 5 0 V 10 0 95 2 8 mA C 120 pF mode VDD 3 0 V 10 0 5 1 5 mA IDD3 STOP VDD 1 8 to 6 0 V 5 µA mode TA 25 C 1 µA VDD 3 0 V 10 0 1 3 µA TA 40 to 40 C 0 1 1 µA Notes 1 The current flowing through the on chip pull up resistor the current during EEPROM writing time and the current when the program threshold port PTH is operating are not i...

Page 52: ... 0 Note 2 1 05 MHz VDD 1 8 to 6 0 V 0 51 1 0 Note 2 1 1 MHz Interrupt input high and tINTH tINTL INT0 IM02 0 Note 3 µs low level width IM02 1 10 µs KR4 to KR7 10 µs RESET low level width tRSL 10 µs Notes 1 The CPU clock Φ cycle time minimum instruction execution time is determined by the time constants of the connected resistor R and capacitor d and the pro cessor clock control register PCC The fi...

Page 53: ...to 85 C 80000 times byte Note Set EWTC 4 to 6 so as to be 18 x 2 8 fCC 4 6 ms fCC 1 0 MHz operation considering the variation of the RC oscillation Comparator Characteristics TA 40 to 85 C VDD 1 8 to 6 0 V Parameter Symbol Conditions MIN TYP MAX Unit Comparison accuracy VACOMP 100 mV Threshold voltage VTH Note Note V PTH input voltage VIPTH 0 VDD V AVREF input voltage VIAVREF 1 8 VDD V Comparator ...

Page 54: ...y Voltage Data Retention Characteristics TA 40 to 85 C Parameter Symbol Test Conditions MIN TYP MAX Unit Release signal set time tSREL 0 µs Oscillation stabilization tWAIT Release by RESET 56 fCC µs wait time Release by interrupt request 512 fCC µs VIH MIN VIL MAX VIH MIN VIL MAX VOH MIN VOL MAX VOH MIN VOL MAX INT0 KR4 to KR7 tINTL tINTH RESET tRSL ...

Page 55: ...ndby release signal on releasing STOP mode by interrupt signal STOP mode Data retention mode Execution of STOP instruction VDD Standby release signal interrupt request tWAIT tSREL HALT mode Operation mode STOP mode Data retention mode Execution of STOP instruction tWAIT tSREL HALT mode Operation mode VDD RESET Internal reset operation ...

Page 56: ...er pin 20 mA For all pins 90 mA Operating ambient TA 40 to 85 C temperature Storage temperature Tstg 65 to 150 C Caution If any of the parameters exceeds the absolute maximum ratings even momentarily the quality of the product may be impaired The absolute maximum ratings are values that may physically damage the products Be sure to use the products within the ratings Capacitance TA 25 C VDD 0 V Pa...

Page 57: ...equency is 4 19 MHz fX 6 0 MHz at 1 8 V VDD 2 0 V set the processor control register PCC to a value other than 0011 or 0010 If the PCC is set to 0011 or 0010 the rated machine cycle time of 1 9 µs is not satisfied 4 If the oscillation frequency is 4 19 MHz fX 6 0 MHz at 2 0 V VDD 2 7 V set the processor control register PCC to a value other than 0011 If the PCC is set to 0011 the rated machine cyc...

Page 58: ... capacitor PBRC6 00A 33 33 PBRC6 00B Model with capacitor Ceramic resonator TA 40 to 80 C Manufacturer Part Number Frequency Recommended Circuit Oscillation Voltage Remark Constant pF Range VDD MHz C1 C2 MIN V MAX V Murata Mfg CSB1000J Note 1 0 100 100 2 0 6 0 Rd 2 2 kΩ Co Ltd CSA2 00MG040 2 0 CST2 00MG040 Model with capacitor CSA4 19MG 4 19 30 30 1 9 CST4 19MGW Model with capacitor CSA4 19MGU 30 ...

Page 59: ... the other recommended resonators Caution The oscillator constants and oscillation voltage range indicate conditions for stable oscilla tion but do not guarantee oscillation frequency accuracy If oscillation frequency accuracy is required for actual circuits it is necessary to adjust the oscillation frequency of the oscillator in the actual circuit Please contact directly the manufacturer of the r...

Page 60: ... VDD 6 0 V 0 0 3VDD V voltage 1 8 V VDD 2 7 V 0 0 1VDD V VIL2 Ports 6 to 8 2 7 V VDD 6 0 V 0 0 2VDD V KRREN RESET 1 8 V VDD 2 7 V 0 0 1VDD V VIH3 X1 0 0 1 V High level VOH VDD 4 5 to 6 0 V IOH 1 0 mA VDD 1 0 V output voltage VDD 1 8 to 6 0 V IOH 100 µA VDD 0 5 V Low level VOL VDD 4 5 to 6 0 V Port 3 IOL 15 mA 0 6 2 0 V output voltage Ports 6 8 0 4 V IOL 1 6 mA VDD 1 8 to 6 0 V IOH 400 µA 0 5 V Hig...

Page 61: ...C2 22 pF mode VDD 3 0 V 10 0 20 0 9 mA IDD3 X1 0 V VDD 1 8 to 6 0 V 5 µA STOP mode TA 25 C 1 µA VDD 3 0 V 10 0 1 3 µA TA 40 to 40 C 0 1 1 µA Notes 1 The current flowing through the on chip pull up resistor the current during EEPROM writing time and the current during the program threshold port PTH operation are not included 2 When the device is operated in the high speed mode by setting the proces...

Page 62: ... to KR7 10 µs RESET low level width tRSL 10 µs Notes 1 The CPU clock Φ cycle time minimum instruction execution time is determined by the oscillation frequency of the con nected resonator or external clock and the processor clock control register PCC The figure on the right shows the cycle time tCY characteristics against the supply voltage VDD when the system clock is used 2 2tCY or 128 fX depend...

Page 63: ... 40 to 70 C 100000 times byte write times TA 40 to 85 C 80000 times byte Comparator Characteristics TA 40 to 85 C VDD 1 8 to 6 0 V Parameter Symbol Conditions MIN TYP MAX Unit Comparison accuracy VACOMP 100 mV Threshold voltage VTH Note Note V PTH input voltage VIPTH 0 VDD V AVREF input voltage VIAVREF 1 8 VDD V Comparator circuit IDD5 When bit 7 of PTHM is set to 1 1 mA current consumption Note T...

Page 64: ...54144 754244 64 Data Sheet U10040EJ2V1DS µPD754244 AC Timing Test Points Excluding X1 Input Clock Timing tXL tXH 1 fX VDD 0 1 V 0 1 V X1 input VIH MIN VIL MAX VIH MIN VIL MAX VOH MIN VOL MAX VOH MIN VOL MAX ...

Page 65: ... Notes 1 The oscillation stabilization wait time is the time during which the CPU operation is stopped to avoid unstable operation at oscillation start 2 217 fx and 215 fx can be selected with mask option 3 Depends on setting of basic interval timer mode register BTM see table below BTM3 BTM2 BTM1 BTM0 Wait Time When fX 4 19 MHz When fX 6 0 MHz 0 0 0 220 fX Approx 250 ms 220 fX Approx 175 ms 0 1 1...

Page 66: ...release signal on releasing STOP mode by interrupt signal STOP mode Data retention mode Execution of STOP instruction VDD Standby release signal interrupt request tWAIT tSREL HALT mode Operation mode STOP mode Data retention mode Execution of STOP instruction tWAIT tSREL HALT mode Operation mode VDD RESET Internal reset operation ...

Page 67: ...EFERENCE VALUES 14 1 µPD754144 10 5 0 1 0 0 5 0 1 0 05 0 01 0 005 0 001 0 1 2 3 4 5 6 7 8 PCC 0011 PCC 0010 PCC 0001 PCC 0000 System clock HALT mode Power Supply Voltage VDD V Power Supply Current I DD mA CL1 CL2 22 kΩ 22 pF IDD vs VDD RC Oscillation R 22 kΩ C 22 pF TA 25 C ...

Page 68: ...44 10 5 0 1 0 0 5 0 1 0 05 0 01 0 005 0 001 0 1 2 3 4 5 6 7 8 PCC 0011 PCC 0010 PCC 0001 PCC 0000 and System clock HALT mode CL1 CL2 5 1 kΩ 120 pF Power Supply Voltage VDD V Power Supply Current I DD mA IDD vs VDD RC Oscillation R 5 1 kΩ C 120 pF TA 25 C ...

Page 69: ...1 0 0 5 0 1 0 05 0 01 0 005 0 001 0 1 2 3 4 5 6 7 8 PCC 0011 PCC 0010 PCC 0001 PCC 0000 System clock HALT mode 22 pF 22 pF X1 X2 Crystal resonator 6 0 MHz Power Supply Voltage VDD V Power Supply Current I DD mA IDD vs VDD System Clock 6 0 MHz Crystal Resonator TA 25 C ...

Page 70: ... 0 5 0 1 0 05 0 01 0 005 0 001 0 1 2 3 4 5 6 7 8 PCC 0011 PCC 0010 PCC 0001 PCC 0000 System clock HALT mode 22 pF 22 pF X1 X2 Crystal resonator 4 19 MHz Power Supply Voltage VDD V Power Supply Current I DD mA IDD vs VDD System Clock 4 19 MHz Crystal Resonator TA 25 C ...

Page 71: ...0 0 5 0 1 0 05 0 01 0 005 0 001 0 1 2 3 4 5 6 7 8 PCC 0011 PCC 0010 PCC 0001 PCC 0000 System clock HALT mode 47 pF 47 pF X1 X2 Crystal resonator 2 0 MHz Power Supply Voltage VDD V Power Supply Current I DD mA IDD vs VDD System Clock 2 0 MHz Crystal Resonator TA 25 C ...

Page 72: ... Frequency f CC MHz 2 0 1 0 0 5 2 0 1 0 0 5 Sample C Sample B Sample A CL1 CL2 22 kΩ 22 pF CL1 CL2 22 kΩ 22 pF CL1 CL2 22 kΩ 22 pF Power Supply Voltage VDD V fCC vs VDD RC Oscillation R 22 kΩ C 22 pF Power Supply Voltage VDD V Power Supply Voltage VDD V System Clock Frequency f CC MHz System Clock Frequency f CC MHz Sample C Sample B Sample A Sample C Sample B Sample A TA 25 C TA 85 C TA 40 C ...

Page 73: ...0 0 5 60 40 20 0 20 40 60 80 100 VDD 5 0 V VDD 6 0 V VDD 3 0 V VDD 3 0 V VDD 2 2 V VDD 1 8 V CL1 CL2 22 kΩ 22 pF CL1 CL2 22 kΩ 22 pF CL1 CL2 22 kΩ 22 pF System Clock Frequency f CC MHz Sample A fCC vs TA RC Oscillation R 22 kΩ C 22 pF System Clock Frequency f CC MHz System Clock Frequency f CC MHz Sample B Sample C Operating Ambient Temperature TA C Operating Ambient Temperature TA C Operating Amb...

Page 74: ...3 4 5 6 7 8 0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8 System Clock Frequency f CC MHz Sample C Sample A Power Supply Voltage VDD V fCC vs VDD RC Oscillation R 5 1 kΩ C 120 pF Power Supply Voltage VDD V Power Supply Voltage VDD V System Clock Frequency f CC MHz System Clock Frequency f CC MHz Sample C Sample B Sample A Sample C Sample B Sample A TA 25 C TA 85 C TA 40 C ...

Page 75: ...V VDD 1 8 V VDD 5 0 V and VDD 6 0 V VDD 3 0 V CL1 CL2 5 1 kΩ 120 pF 2 0 1 0 0 5 60 40 20 0 20 40 60 80 100 VDD 5 0 V VDD 6 0 V VDD 3 0 V VDD 2 2 V VDD 1 8 V System Clock Frequency f CC MHz Sample A System Clock Frequency f CC MHz System Clock Frequency f CC MHz Sample B Sample C Operating Ambient Temperature TA C Operating Ambient Temperature TA C Operating Ambient Temperature TA C fCC vs TA RC Os...

Page 76: ...31 MAX 0 004 0 004 0 071 MAX 0 061 0 002 0 303 0 012 0 043 0 005 0 050 T P P20GM 50 300B C 5 P 3 3 7 NOTE Each lead centerline is located within 0 12 mm 0 005 inch of its true position T P at maximum material condition D 0 42 0 017 0 08 0 07 K 0 22 0 009 0 08 0 07 L 0 6 0 2 0 024 0 10 3 7 3 0 004 0 008 0 009 0 003 0 004 0 003 0 004 detail of lead end M 1 10 11 20 I 5 6 0 2 0 220 0 009 0 008 A B H ...

Page 77: ...P20GM 65 300B 3 ITEM MILLIMETERS INCHES A B C D E F G H I J 0 65 T P 2 0 MAX 1 7 0 1 8 1 0 3 0 575 MAX K L 0 12 0 5 0 2 1 0 0 2 6 1 0 2 0 15 M 0 10 0 32 0 125 0 075 N 0 10 0 05 0 023 MAX 0 013 0 005 0 003 0 079 MAX 0 067 0 319 0 012 0 240 0 008 0 039 0 006 0 020 0 005 0 004 0 008 0 009 0 026 T P P 3 3 0 004 0 005 0 004 0 002 6 7 0 3 0 264 0 012 0 013 1 Controlling dimension millimeter S 0 003 0 00...

Page 78: ...tial heating Pin temperature 350 C max Time 3 seconds max per pin row Caution Do not use different soldering methods together except for partial heating Remark For soldering methods and conditions other than those recommended above contact an NEC Electronics sales representative 2 µPD754144GS xxx GJG 20 pin plastic shrink SOP 300 mil 0 65 mm pitch Soldering Method Soldering Conditions Recommended ...

Page 79: ...pening the dry pack store it at 25 C or less and 65 RH or less for the allowable storage period Caution Do not use different soldering methods together except for partial heating Remark For soldering methods and conditions other than those recommended above contact an NEC Electronics sales representative 4 µPD754244GS xxx BA5 A 20 pin plastic SOP 300 mil 1 27 mm pitch Soldering Method Soldering Co...

Page 80: ...ns 3 3 5 µPD754144GS xxx BA5 A 20 pin plastic SOP 300 mil 1 27 mm pitch µPD754144GS xxx GJG A 20 pin plastic shrink SOP 300 mil 0 65 mm pitch µPD754144GS xxx GJG A 20 pin plastic shrink SOP 300 mil 0 65 mm pitch Undefined Remark Products with A at the end of the part number are lead free products ...

Page 81: ...Total 13 System clock oscillator RC oscillator Ceramic crystal oscillator resistor and capacitor are connected externally Start up time after reset 56 fCC 2 17 fX 2 15 fX can be 2 15 fX selected by mask option Standby mode release time 2 9 fCC 2 20 fX 2 17 fX 2 15 fX 2 13 fX can be selected by the setting of BTM Timer 4 channels 8 bit timer counter 3 channels can be used as 16 bit timer counter Ba...

Page 82: ...µS5A13RA75X Ver 3 30 to 5 inch 2HD µS5A10RA75X Ver 6 2Note IBM PC ATTM and Refer to 3 5 inch 2HC µS7B13RA75X compatible machines OS for IBM PC 5 inch 2HC µS7B10RA75X Device file Host machine Part number OS Distribution media product name PC 9800 series MS DOS 3 5 inch 2HD µS5A13DF754244 Ver 3 30 to 5 inch 2HD µS5A10DF754244 Ver 6 2Note IBM PC AT and Refer to 3 5 inch 2HC µS7B13DF754244 compatible ...

Page 83: ...5001 R By connecting the host machine efficient debugging can be made IE 75300 R EM Emulation board for evaluating the application systems that use the µPD754244 It must be used with the IE 75000 R or IE 75001 R EP 754144GS R Emulation probe for the µPD754244GS It must be connected to IE 75000 R or IE 75001 R and IE 75300 R EM It is supplied with the flexible boards EV 9500GS 20 supporting 20 pin ...

Page 84: ...e supported OS Version PC DOSTM Ver 5 02 to Ver 6 3 J6 1 VNote to J6 3 VNote MS DOS Ver 5 0 to Ver 6 22 5 0 V Note to J6 2 V Note IBM DOSTM J5 02 VNote Note Supported only English mode Caution Ver 5 0 and later have the task swap function but it cannot be used for operating systems above ...

Page 85: ...416 IE 75300 R EM User s Manual U11354J U11354E EP 754144GS R User s Manual U10695J U10695E Software RA75X Assembler Package User s Manual Operation EEU 731 EEU 1346 Language EEU 730 EEU 1363 Other related documents Document Name Document Number Japanese English IC Package Manual C10943X Semiconductor Device Mounting Technology Manual C10535J C10535E Quality Grades on NEC Semiconductor Devices C11...

Page 86: ...t tools including work benches and floors should be grounded The operator should be grounded using a wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken for PW boards with mounted semiconductor devices STATUS BEFORE INITIALIZATION Power on does not necessarily define the initial status of a MOS device Immediately after the power source is turn...

Page 87: ...Seoul Branch Seoul Korea Tel 02 558 3737 NEC Electronics Shanghai Ltd Shanghai P R China Tel 021 5888 5400 NEC Electronics Taiwan Ltd Taipei Taiwan Tel 02 2719 2377 NEC Electronics Singapore Pte Ltd Novena Square Singapore Tel 6253 8311 J05 6 NEC Electronics Europe GmbH Duesseldorf Germany Tel 0211 65030 Sucursal en España Madrid Spain Tel 091 504 27 87 Vélizy Villacoublay France Tel 01 30 67 58 0...

Page 88: ...inimize risks of damage to property or injury including death to persons arising from defects in NEC Electronics products customers must incorporate sufficient safety measures in their design such as redundancy fire containment and anti failure features NEC Electronics products are classified into the following three quality grades Standard Special and Specific The Specific quality grade applies o...

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