Connector Pin Assignments B-9
IDE INTERFACE CONNECTORS
All signal levels in the IDE interface are TTL compatible. A logic 1 is a signal whose
voltage level is between 2.0 and 5.0 V. A logic 0 is a signal measuring between 0.00 V and
0.70 V.
The two system board IDE connectors are physically identical. Electrically, the primary
IDE/PCI bus IDE connector is faster and the secondary IDE/PCI connector is slower.
Table B-10 provides the IDE pin assignments. All signals on the Host interface have the
prefix HOST. All negatively active signals are further prefixed with a “-” designation. All
positively active signals are prefixed with a “+” designation.
Table B-10 IDE/PCI Connector Pin Assignments
Pin
Description
Pin
Description
1
Reset IDE
2
Ground
3
Host data 7
4
Host data 8
5
Host data 6
6
Host data 9
7
Host data 5
8
Host data 10
9
Host data 4
10
Host data 11
11
Host data 3
12
Host data 12
13
Host data 2
14
Host data 13
15
Host data 1
16
Host data 14
17
Host data 0
18
Host data 15
19
Ground
20
Key
21
DDRQ0 (DDRQ1)
22
Ground
23
I/O write#
24
Ground
25
I/O read#
26
Ground
27
IOCHRDY
28
P_ALE (Cable select pullup)
29
DDACK# (DDACK1#)
30
Ground
31
IRQ 14 (IRQ 15)
32
Reserved
33
Address 1
34
Reserved
35
Address 0
36
Address 2
37
Chip select 1P# (Chip select 1S#)
38
Chip select 3P# (Chipselect 3S#)
39
Activity#
40
Ground
Note: Signal names in parentheses ( ) are for the secondary IDE connector.
Summary of Contents for DIRECTION L - SERVICE
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