Vector-LP Radio Beacon Transmitter Technical Instruction Manual
Page 6-23 (6-24 Blank)
Section 6 Theory of Operation
Issue 1.1
6.6.1.2.2 Gate Bias Drive Signal
U7, Q2 and associated components
generate a 15 V square wave at 263 kHz to
drive the gate bias drive in the modulator.
6.6.1.2.3 Switch Mode Supply Control
Decodes the serial control (B+ settings) from
the control/display PWB and outputs the
settings using darlington transistor U1.
6.6.1.3 MODULATOR
See Figure SD-22. The modulator (A5) is a
logic level converter that converts the low
level (0 to 15 V) logic of the
PDM
input to a
high level (0-B+) logic
PDM (B+)
output.
6.6.1.3.1 13 V Power Supply
The 15 V
LO
output (pin 1) of FET driver U1
is full-wave rectified by bridge rectifier CR1
through CR4, at the PDM frequency. The
resultant dc voltage is filtered by capacitor
C7 and limited to 13 V by zener diode CR5.
The power supply's less positive output is
referenced to the source terminal of power
FET Q1 via resistor R7. Therefore, the
positive output is always 13 V higher than
the voltage on the FET source terminal. The
13 V output is applied to U1’s V
B
(+) and V
S
(-) inputs as the switched gate drive for the
FETs. Transformer T1 provides isolation
between the high and low level signals.
6.6.1.3.2 FET Driver
FET driver U1 is an integrated circuit
configured to produce outputs as follows:
x
When the PDM signal applied to the H
IN
input is high (15 V), the H
O
output is the dc
voltage applied to the V
B
input.
x
When the PDM signal applied to the H
IN
input is low (0 V), the H
O
output is the
reference voltage applied to the V
S
input.
The H
O
output, which contains the PDM data,
is applied to the gate of power MOSFET Q1
as its on/off control.
6.6.1.3.3 B+ Switching MOSFET
Power MOSFET Q1 is connected to switch
the B+ voltage at the on/off ratio of the PDM
data on U1's H
O
output, which is applied to its
gate. The resultant
PDM (B+)
output contains
the PDM data applied to J2-7 at a high (0-B+)
logic level. Free-wheeling diode CR6
prevents negative overshoot by providing
current flow when MOSFET Q1 is off.
6.6.1.4 MODULATOR FILTER PWB
See Figure SD-22. The modulator filter PWB
(A4) consists of inductors L1 and L2 and
capacitors C1 and C3 as well as C2 of the
power amplifier (A3). These components form
a low pass filter that passes the audio
components but rejects the PDM frequency.
When no modulating audio information is
present, the
PA Volts
output will be a dc
voltage equal to the modulator input voltage
multiplied by the duty cycle of the PDM (B+)
signal. Capacitor C3 in conjunction with L2 is
resonant at a frequency to provide optimal
rejection of the PDM frequency.
6.6.1.5 POWER AMPLIFIER
See Figure SD-22. The power amplifier (A3)
uses two parallel pairs of MOSFETs to
produce an unfiltered, modulated RF output.
Q1 through Q4 are connected as cascode or
‘H’ bridge class ‘D’ amplifiers, which switch
the
PA volts
at the RF drive frequency (see
Figure 6-6 for a description of class D
operation). Transformer T1 splits the
RF
drive
signal and applies it, through buffer
amplifier U1 (fused by F1) to the MOSFETs
with the required phase relationship. Diodes
CR1 through CR4 prevent the output of the
RF amplifier from going negative. Transistor
Q5 and associated components detect the
RF drive level and provide an alarm signal to
the control/display PWB. Resistors R5
through R7 provide a
PA Volts Sample
for
front panel monitoring.
6.6.1.6 RF TRANSFORMER
RF transformer T1 provides impedance
matching between the power amplifier
output and the RF filter PWB.
