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4.0 Register Set
(Continued)
DP83816
4.1.4 Configuration Latency Timer Register
This register gives status and controls such miscellaneous functions as BIST, Latency timer and Cache line size.
DP83816 Bus Master Operations:
Independent of cache line size, the DP83816 will use the following PCI commands for bus mastered transfers:
0110 - Mem Read
for all read cycles,
0111 - Mem Write
for all write cycles.
4.1.5 Configuration I/O Base Address Register
This register specifies the Base I/O address which is required to build an address map during configuration. It also
specifies the number of bytes required as well as an indication that it can be mapped into I/O space.
Tag:
CFGLAT
Size:
32 bits
Hard Reset:
00000000h
Offset:
0Ch
Access:
Read Write
Soft Reset:
Unchanged
Bit
Bit Name
Description
31
BISTCAP
BIST Capable
Reads will always return 0.
30
BISTEN
BIST Enable
Reads will return a 0, writes are ignored.
29-16
Reserved
Reads will return a 0, writes are ignored.
15-8
LAT
Latency Timer
Set by software to the number of PCI clocks that DP83816 may hold the PCI bus.
7-0
CLS
Cache Line Size
Ignored by DP83816.
Tag:
CFGIOA
Size:
32 bits
Hard Reset:
00000001h
Offset:
10h
Access:
Read Write
Soft Reset:
Unchanged
Bit
Bit Name
Description
31-8
IOBASE
Base I/O Address
This is set by software to the base I/O address for the Operational Register Map.
7-2
IOSIZE
Size indication
Read back as 0. This allows the PCI bridge to determine that the DP83816 requires 256 bytes of I/O
space.
1
Unused
(reads return 0).
0
IOIND
I/O Space Indicator
Set to 1 by DP83816 to indicate that DP83816 is capable of being mapped into I/O space. Read Only.
Summary of Contents for MacPHYTER-II DP83816
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