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4.0 Register Set
(Continued)
DP83816
4.3.10 MII Interrupt Control Register
This register implements the MII Interrupt PHY Specific Control register. Sources for interrupt generation include: Link
State Change, Jabber Event, Remote Fault, Auto-Negotiation Complete or any of the counters becoming half-full. Note
that the TINT bit operates independently of the INTEN bit. In other words, INTEN does not need to be active to generate
the test interrupt.
4.3.11 MII Interrupt Status and Misc. Control Register
This register implements the MII Interrupt PHY Control and Status information. These Interrupts are PHY based events.
When any of these events occur and its respective bit is not masked, and MICR:INTEN is enabled, the interrupt will be
signalled in ISR:PHY.
Tag:
MICR
Size:
16 bits
Hard Reset:
0000h
Offset:
00C4h
Access:
Read Write
Bit
Bit Name
Description
15:2
Reserved
Reserved
: Writes ignored, Read as 0
1
INTEN
Interrupt Enable:
1 = Enable event based interrupts
0 = Disable event based interrupts
0
TINT
Test Interrupt:
Forces the PHY to generate an interrupt at the end of each management read to facilitate interrupt testing.
1 = Generate an interrupt
0 = Do not generate interrupt
Tag:
MISR
Size:
16 bits
Hard Reset:
0000h
Offset:
00C8h
Access:
Read Write
Bit
Bit Name
Description
15
MINT
MII Interrupt Pending:
Default: 0, RO/COR
1 = Indicates that an interrupt is pending and is cleared by the current read.
0 = no interrupt pending
14
MSK_LINK
Mask Link:
When this bit is 0, the change of link status event will cause the interrupt to be seen by the ISR.
13
MSK_JAB
Mask Jabber:
When this bit is 0, the Jabber event will cause the interrupt to be seen by the ISR.
12
MSK_RF
Mask Remote Fault:
When this bit is 0, the Remote Fault event will cause the interrupt to be seen by the
ISR.
11
MSK_ANC
Mask Auto-Neg. Complete:
When this bit is 0, the Auto-negotiation complete event will cause the inter-
rupt to be seen by the ISR.
10
MSK_FHF
Mask False Carrier Half Full:
When this bit is 0, the False Carrier Counter Register half-full event will
cause the interrupt to be seen by the ISR.
9
MSK_RHF
Mask Rx Error Half Full:
When this bit is 0, the Receive Error Counter Register half-full event will cause
the interrupt to be seen by the ISR.
8:0
Reserved
Reserved
: Writes ignored, Read as 0
Summary of Contents for MacPHYTER-II DP83816
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