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4.0 Register Set
(Continued)
DP83816
4.3.12 False Carrier Sense Counter Register
This counter provides information required to implement the “FalseCarriers” attribute within the MAU managed object
class of Clause 30 of the IEEE 802.3u specification.
4.3.13 Receiver Error Counter Register
This counter provides information required to implement the “SymbolErrorDuringCarrier” attribute within the PHY
managed object class of Clause 30 of the IEEE 802.3u specification.
4.3.14 100 Mb/s PCS Configuration and Status Register
Tag:
FCSCR
Size:
16 bits
Hard Reset:
0000h
Offset:
00D0h
Access:
Read Write
Bit
Bit Name
Description
15:8
Reserved
Reserved:
Writes ignored, Read as 0
7:0
FCSCNT[7:0]
False Carrier Event Counter:
Default: 0, RW/COR
This 8-bit counter increments on every false carrier event. This counter sticks when it reaches its max
count (FFh).
Tag:
RECR
Size:
16 bits
Hard Reset:
0000h
Offset:
00D4h
Access:
Read Write
Bit
Bit Name
Description
15:8
Reserved
Reserved:
Writes ignored, Read as 0
7:0
RXERCNT[7:0]
RXER Counter:
Default: 0, RW / COR
This 8-bit counter increments for each receive error detected. when a valid carrier is present and there
is at least one occurrence of an invalid data symbol. This event can increment only once per valid
carrier event. If a collision is present, the attribute will not increment. The counter sticks when it
reaches its max count.
Tag:
PCSR
Size:
16 bits
Hard Reset:
0100h
Offset:
00D8h
Access:
Read Write
Bit
Bit Name
Description
15:13
Reserved
Reserved:
Writes ignored, Read as 0
12
BYP_4B5B
Bypass 4B/5B Encoding:
1 = 4B5B encoder functions bypassed
0 = Normal 4B5B operation
11
FREE_CLK
Receive Clock:
1 = RX_CK is free-running
0 = RX_CK phase adjusted based on alignment
10
TQ_EN
100 Mb/s True Quiet Mode Enable:
1 = Transmit True Quiet Mode
0 = Normal Transmit Mode
9
SD_FORCE_B
Signal Detect Force:
1 = Forces Signal Detection
0 = Normal SD operation
Summary of Contents for MacPHYTER-II DP83816
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