7.0 DC and AC Specifications
(Continued)
94
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DP83816
7.2.6 PCI Bus Cycles
The following table parameters apply to
ALL
the PCI Bus Cycle Timing Diagrams contained in this section.
PCI Configuration Read
Number
Parameter
Min
Max
Units
7.2.6.1
Input Setup Time
7
ns
7.2.6.2
Input Hold Time
0
ns
7.2.6.3
Output Valid Delay
2
11
ns
7.2.6.4
Output Float Delay (t
off
time)
28
ns
7.2.6.5
Output Valid Delay for REQN - point to point
2
12
ns
7.2.6.6
Input Setup Time for GNTN - point to point
10
ns
PCICLK
FRAMEN
AD[31:0]
C/BEN[3:0]
IRDYN
TRDYN
DEVSELN
PAR
PERRN
Addr
Data
IDSEL
T1
T2
T1 T2
T4
T1
T1
T1
T2
T2
T2
T3
T4
T4
T4
T3
T1 T2
T1
T2
T3
T3
T1
Cmd
BE
T2
T3
T3
T1
Summary of Contents for MacPHYTER-II DP83816
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