programmable, which is useful if you are importing signals from multiple sources with
different voltage swings.
Using Front Panel PFIs as Single Ended Outputs
The front panel PFI outputs are +3.3 V drivers with 50 Ω output impedance. The outputs can
drive 50 Ω loads, such as a 50 Ω coaxial cable with a 50 Ω receiver. This cable configuration
is the recommended setup to minimize reflections. With this configuration, the receiver sees a
1.6 V step—a +3.3 V step split across the 50 Ω resistors at the source and the
destination.
You also can drive a 50 Ω cable with a high-impedance load. The destination sees a single step
to +3.3 V, but the source sees a reflection. This cable configuration is acceptable for low-
frequency signals or short cables.
You can independently select the output signal source for each of the PFI lines from one of the
following sources:
•
Another PFI<0..5>
•
Another PFI pair in LVDS mode
•
PXI_TRIG<0..7>
•
PXI_STAR
•
Global software trigger
•
PFI synchronization clock
•
PXIe_DSTARB
•
Steady logic high or low
The PFI synchronization clock may be any of the following signals:
•
Clock Generation
•
PXI_CLK10
•
PXIe_CLK100
•
CLKIN
•
Any of the previously listed signals divided by the first frequency divider (2
n
, up to 512).
•
Any of the previously listed signals divided by the second frequency divider (2
m
, up to
512)
Refer to the
section for more information on the synchronization
clock.
Note
The PFI synchronization clock is the same for all routing operations in which
PFI<0..5> or PFI_LVDS<0..2> is defined as the output, although the divide-down
ratio for this clock (full rate, first divider, second divider) may be chosen on a per
route basis.
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PXIe-6674 User Manual