Table 3. Signal Descriptions (Continued)
Signal Name
Direction
Description
PXIe_STARB
In (from
chassis)
The PXIe_DSTARB lines connect the system timing
module to each peripheral slot in a PXI Express chassis,
allowing the system timing module to send out high speed
triggers to every slot. PXI_DSTARB uses differential
LVDS signaling and is capable of sending out higher
speed trigger signals.
PXIe_DSTARC
Out (to
chassis)
The PXIe_DSTARC lines connect each peripheral slot in a
PXI Express chassis to the system timing module,
allowing the system timing module to receive high speed
clock and trigger signals from every slot. PXIe_DSTARC
uses differential LVDS signaling.
The remainder of this chapter describes how these signals are used, acquired, and generated by
the PXIe-6674 hardware, and explains how you can route the signals between various
locations to synchronize multiple measurement devices and PXI chassis.
Generating and Routing Clocks
The PXIe-6674 can generate a clock using the onboard clock generation circuitry. The
following section describes the clock generation functionality and resources available on the
PXIe-6674 for routing clock signals.
Clock Generation
The PXIe-6674 includes built-in advanced clock generation circuitry for generating clock
signals below 1 Hz to 1 GHz with very fine frequency resolution. The clock generation
circuitry is based on a direct digital synthesis (DDS) with an 800 MHz reference phase locked
to PXIe_CLK100. This allows the DDS to generate a 150 MHz to 300 MHz signal with
microhertz resolution. The output from the DDS can then be divided down to lower
frequencies, used directly, or multiplied up using a phase locked voltage controlled oscillator.
The individual components which make up the clock generation circuitry are controlled by NI-
Sync software, which allows the user to simply specify the frequency they wish the clock
generation circuitry to produce. NI-Sync will then configure the clock generation circuitry to
give the closest possible frequency match to the requested frequency and do so with the
configuration that gives the lowest possible phase noise. The user may request a clock
frequency up to 1 GHz (frequencies beyond 1 GHz are possible but performance is not
specified). The precision of the frequency generated is that of the DDS scaled up or down for
any division or multiplication done to generate the requested frequency, as shown in
on page 13.
12
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PXIe-6674 User Manual
