Table 3. Signal Descriptions (Continued)
Signal Name
Direction
Description
PFI<0..5>
In/Out (to/
from front
panel)
The single ended Programmable Function Interface (PFI)
pins on the PXIe-6674 route timing and triggering signals
between multiple PXI Express chassis. A wide variety of
input and output signals can be routed to or from the PFI
lines.
PFI_LVDS<0..2> In/Out (to/
from front
panel)
The LVDS Programmable Function Interface can be used
to route timing and triggering signals between multiple
PXI Express chassis. The use of LVDS logic allows much
faster speeds than can be achieved with the single ended
PFIs. The LVDS PFIs, when used as outputs, can be
sourced from the PXIe_DSTARA network, the FPGA, or
the clock generation circuitry. As inputs, the LVDS PFIs
can be routed to the PXIe_DSTARA network and to the
FPGA.
PXI_TRIG<0..7> In/Out (to/
from chassis)
The PXI trigger bus consists of eight digital lines shared
among all slots in the PXI Express chassis. The
PXIe-6674 can route a wide variety of signals to and from
these lines.
Note
PXI_TRIG<0..5> are also known as
RTSI<0..5> in some hardware devices and
APIs. However, PXI_TRIG<6..7> are not
identical to RTSI<6..7>.
PXI_STAR
In/Out (to/
from chassis)
The PXI star trigger bus connects the system timing slot to
other peripheral slots in a star configuration. The electrical
paths of each star line are closely matched to minimize
intermodule skew. The PXIe-6674 connects to the
PXI_STAR line for the slot the device is located in.
PXIe_DSTARA
In (from
chassis)
The PXIe-DSTARA lines connect the system timing
module to each peripheral slot in a PXI Express chassis,
allowing the system timing module to distribute a clock
signal to every slot. PXIe-DSTARA uses differential
LVPECL signaling and is capable of high speed clock
distribution.
PXIe-6674 User Manual
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© National Instruments
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