The frequency on the PXI triggers should not exceed 5 MHz to preserve signal integrity. The
signals do not reach each slot at precisely the same time. A difference of several nanoseconds
between slots can occur in an eight-slot chassis. However, this delay is not a problem for many
applications.
You can independently select the output signal source for each PXI trigger line from one of the
following sources:
•
PFI<0..5>
•
PFI_LVDS<0..2>
•
PXI_TRIG<0..7>
•
PXI_STAR
•
Global software trigger
•
Backplane synchronization clock
•
PXIe_DSTARB
•
Steady logic high or low.
The backplane synchronization clock may be any of the following signals:
•
Clock Generation
•
PXI_CLK10
•
PXIe_CLK100
•
CLKIN
•
Any of the previously listed signals divided by the first frequency divider (2
n
, up to 512)
•
Any of the previously listed signals divided by the second frequency divider (2
m
, up to
512)
Refer to the
section for more information about the
synchronization clock.
Note
The backplane synchronization clock is the same for all routing operations in
which PXI_TRIG<0..7>, PXIe_DSTARC, or PXI_STAR is defined as the output,
although the divide-down ratio for this clock (full rate, first divider, second divider)
may be chosen on a per route basis.
Using the PXI Star Trigger
There are up to 17 PXI star triggers per chassis. Each trigger line is a dedicated connection
between the system timing slot and one other slot. The PXI Specification, Revision 2.1,
requires that the propagation delay along each star trigger line be matched to within 1 ns. A
typical upper limit for the skew in most NI PXI Express chassis is 500 ps. The low skew of the
PXI star trigger bus is useful for applications that require triggers to arrive at several modules
nearly simultaneously.
The star trigger lines are bidirectional, so signals can be sent to the system timing slot from a
module in another slot or from the system timing slot to the other module.
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PXIe-6674 User Manual
