© National Instruments
|
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NI High-Speed Serial Instruments User Manual
For more information about how to use Eye Scan VIs, refer to the
NI High-Speed Serial
Instruments Help
.
Compiling LabVIEW FPGA VIs
You may need to purchase and install additional licenses to compile FPGA designs that
incorporate licensed cores from Xilinx or third-party IP vendors. Refer to
UG 973: Vivado
Design Suite: Release Notes, Installation, and Licensing
at
xilinx.com
for information about
managing licenses.
The high-speed serial devices include large FPGA devices that require a 64-bit compile worker.
Refer to the
NI High-Speed Serial Readme
for more information about what platforms to use to
compile bitfiles.
If you are using LabVIEW FPGA 2014 or later, you cannot add additional licenses to remote
compile workers in the NI LabVIWEW FPGA Compile Cloud Service. You cannot use
NI LabVIEW FPGA Compile Cloud Service to compile designs that incorporate Xilinx or
other third-party licensed cores.
LabVIEW and System Integration
The following sections contain information about how to integrate your high-speed serial system
in the LabVIEW application development environment.
Download, Reset, and Run Side Effects in the
LabVIEW FPGA Host Interface
When the high-speed serial device FPGA loads, it performs a power-on self-configuration
sequence that configures various on-board hardware. This configuration occurs at the following
times:
•
At device power-up after the bitfile loads.
•
At the first time
Run
is called after a new bitfile is downloaded and the bitfile is not set to
Run on Load
.
•
When
Run
is called after
Reset
.
For more information about
Run
,
Reset
, and other Invoke methods, refer to the
LabVIEW FPGA
Module Help
.
Note
When self-configuration executes, the clocking configuration enters an
indeterminate state. When the clocking configuration is in an indeterminate state,
you cannot rely on clocking stability from the clocking and routing hardware on the
high-speed serial device.
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