© National Instruments
|
8-1
8
Developing Applications for
the High-Speed Serial Device
This chapter provides information about how to develop applications for the high-speed serial
device, including information about creating socketed CLIP and using LabVIEW.
Development Flow
Refer to the following diagram for an overview of the high-speed serial development process.
Figure 8-1.
High-Speed Serial Development Process
If the sample project code is sufficient for your application, you do not have to modify the IP
core, update the VHDL CLIP wrapper, or refresh the CLIP.
Socketed CLIP Development
This section provides steps for creating socketed CLIP for use with your application. Socketed
CLIP provides the following functionality:
•
Allows you to insert HDL IP into an FPGA target, enabling VHDL code to communicate
directly with an FPGA VI.
•
Allows the CLIP to communicate directly with circuitry external to the FPGA.
•
Allows your IP to communicate directly with both the FPGA VI and the external FPGA
module connector interface.
You can develop socketed CLIP either by using the Xilinx Vivado tools, or by exporting a
LabVIEW FPGA VI as a Vivado Design Suite project.
Upd
a
te L
ab
VIEW
FPGA
a
nd
L
ab
VIEW De
s
ktop
a
pplic
a
tion code
Upd
a
te VHDL
CLIP Wr
a
pper
Modify/regener
a
te
IP core
us
ing
Xilinx Viv
a
do
Cre
a
te IP core
us
ing Xilinx Viv
a
do
or licen
s
e/
bu
y from
third p
a
rty
Write c
us
tom
protocol core IP
Cre
a
te
Sa
mple
Project
Upd
a
te L
ab
VIEW
FPGA project
a
nd
refre
s
h CLIP
Write VHDL
CLIP Wr
a
pper
Cre
a
te L
ab
VIEW
FPGA project
a
nd
import CLIP
Write L
ab
VIEW
FPGA
a
nd
L
ab
VIEW De
s
ktop
a
pplic
a
tion code
Deploy
Applic
a
tion
No
Ye
s
Comp
a
ti
b
le
IP commerci
a
lly
a
v
a
il
ab
le?
No
No
Ye
s
S
t
a
rt
Sa
mple
Project Exi
s
t
s
for
Protocol?
Export
to
Viv
a
do
Export
to
Viv
a
do
Export
to
Viv
a
do
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