8-10
|
ni.com
Chapter 8
Developing Applications for the High-Speed Serial Device
domain in which they are written on the LabVIEW diagram. In rare cases where
crossing clock domains is desirable, refer to KnowledgeBase
6OB8E8FM
at
ni.com/kb
for more information about how to write timing constraints between the
CLIP and the LabVIEW diagram in order to specify timing exceptions on these paths
and achieve timing closure. Note that data corruption might still occur when crossing
clock domains.
Documenting Your IP
NI recommends documenting the behavior of your CLIP. Refer to the following guidelines for
information about how to document your CLIP and how documenting your CLIP can affect the
rest of your design:
•
Document the endianness of your CLIP in order to properly interface your CLIP to the
LabVIEW FPGA diagram. Refer to the
Writing a VHDL Wrapper Around the Protocol IP
Core
section of this chapter for more information about how CLIP endianess affects the
design process.
•
Clearly define the portion of your entity interface that is facing the diagram, and which
portion of your entity is facing the front panel.
•
Clearly define your LED behavior.
•
Document the connector signals by describing which signals are used, which signals are
unused, and the manner in which the signal is used. Signal use can affect which ports are
active with your IP and the behavior of cables upon insetion and removal.
•
Use the DebugClks signal to determine the health of the internal clocks being sent to the IP.
Define which bits of the 4-bit vector correspond to the clock being monitored.
•
Document how you integrate AXI4-Lite signals with LabVIEW data types. Some
AXI4-Lite signals do not integrate easily with LabVIEW data types; for example, address
ports can have widths of 11, but LabVIEW only provides addresses with widths of 8, 16,
32, and 64. Additionally, the AXI4-Lite and AXI4-Stream adapters are configured for use
with fixed-point I/O.
•
Document how clocks are used and how they are routed in your CLIP for use with the IP.
You must route clocks to the diagram for use with the single-cycle timed loop (SCTL) in
LabVIEW FPGA.
•
Document the address map of individual components within any AXI4-Lite interfaces.
Improving Performance in Larger Designs through
Enable Chain Removal
By default, LabVIEW adds code to the FPGA code to enforce data flow. This code
addition is referred to as the enable chain. In larger applications, the enable chain can create
routing congestion and limit performance. You can remove the enable chain under certain
circumstances. Refer to
Improving Timing Performance in Large Designs (FPGA Module)
in the
LabVIEW FPGA Module Help
for more information about how to remove enable chains and
when to do so.
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