CLIP Signal Name
Direction
Data Type
Description
for
additional information.
The FPGA delay is
restricted to the
Align_Delay
tap value
as the lower limit and
to 511 delay taps as the
upper limit. Refer to
the UG571 - Ultrascale
Architecture SelectIO
Resources user guide
for
additional information
on the
Align_Delay
tap value.
The PXIe-6569 CLIP
enforces the upper
delay limit by
preventing any further
delay increments when
the 511 tap delay
value is reached.
The PXIe-6569 CLIP
also enforces the
lower delay limit by
preventing any further
delay decrements
when the
Align_Delay
tap value is reached.
TX/RX Delay Done
From CLIP
Boolean
Reports when an
increment/decrement
operation has
completed.
Rx Bitslip
To CLIP
Boolean
Rotates the U8
captured data by one
bit when asserted. This
signal can be used to
© National Instruments
33
PXIe-6569 Getting Started Guide
