Socketed CLIP Signals
Each LVDS configuration variant of the PXIe-6569 has a different set of signals you
must use in the socketed CLIP. Some CLIP signals and data types are specific to
the module variant being used. The following table lists the term used in the CLIP
signals to represent each associated module variant.
LVDS Configuration Reference in CLIP
PXIe-6569 Variant
Half-In, Half-Out (HIHO)
32 LVDS In, 32 LVDS Out
All In
64 LVDS In
All Out
64 LVDS Out
Refer to
for PXIe-6569 connector signals and the
associated FPGA signal information.
PXIe-6569 Basic Socketed CLIP Signals
CLIP Signal Name
Direction
Data Type
Description
IO Ready
From CLIP
Boolean
Indicates successful
configuration of the
IO module with the
current clocking mode
settings.
IO Error
From CLIP
I32
Returns IO module
errors, to be reported
by the driver.
SE_Data_Output_Enab
le
To CLIP
Boolean
Provides read/write
access to all single-
ended channels.
SE_Data_Output_Enab
le values:
■
1—Use
SE_Data_Wr to
SE_Data_Rd
From CLIP
Boolean
SE_Data_Wr
To CLIP
Boolean
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PXIe-6569 Getting Started Guide
