NI Example Finder FlexRIO Example
Description
Show All FlexRIO with Integrated IO Hardware.vi Queries and displays a set of hardware
properties from all FlexRIO with Integrated I/O
devices in a chassis.
Vivado Export Getting Started Ultrascale.lvproj Demonstrates how to export your LabVIEW
FPGA project into Vivado in order to develop
your FPGA design in the Vivado ADE.
Read-Write Calibration Data.vi
Demonstrates how to read and write calibration
data and metadata into the storage space of
FlexRIO with Integrated I/O devices.
FPGA Carrier Block Diagram
Synchronization
Bus Interface
FPGA
DRAM
Bank 1
+12 V
I/O
Module
Mezz
anine
Connec
tor
Flash
Power Supplies
+12 V, +3.3 V
PXIe
Backplane
Module Clocking
GPIO
Configuration, GPIO
+1.8 V
DStarB, DStarC
PXI Triggers
PXIe_CLK100
PXI_CLK10
Reference
Clock
DRAM
Bank 0
PXIe-6569 I/O Block Diagram
© National Instruments
21
PXIe-6569 Getting Started Guide
