© National Instruments
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2-19
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Case 2
—If an additional line on the bus also has a transition during the filter clock period,
the change is not propagated until the next filter clock edge, as shown in Figure 2-15.
Figure 2-15.
Case 2
Figure 2-16 illustrates the difference between line and bus filtering.
Figure 2-16.
Line and Bus Filtering
Connecting Digital I/O Signals
The DIO signals, P0.<0..31> and P1.<0..7> are referenced to D GND. Each line can be
individually programmed as an input or output. Figure 2-17 shows P1.<0..3> configured for
digital input and P1.<4..7> configured for digital output. Digital input applications include
receiving TTL signals and sensing external device states, such as the state of the switch shown
2A With line filtering, filtered input A would ignore the glitch on digital input P0.B and transition after two filter
clocks.
3A Filtered input A goes high when sampled high for two consecutive filter clocks and transitions on the next
filter edge because digital input P0.B glitches.
Digit
a
l Inp
u
t P0.A
Digit
a
l Inp
u
t P0.B
Filter Clock
Filtered Inp
u
t A
Filtered Inp
u
t B
Not
S
t
ab
le
Not
S
t
ab
le
Digit
a
l Inp
u
t P0.A
Digit
a
l Inp
u
t P0.B
Filter Clock
Filtered Inp
u
t A
Filtered Inp
u
t B
1A
2A
3
A
