National Instruments NI 5791R User Manual And Specifications Download Page 9

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Block Diagram

The following figure shows the NI 5791 block diagram.

Figure 3. NI 5791 Block Diagram

ADC

14 bit

TI ADS4246

Noise Reject

LPF

4.4 GHz

LPF

4.4 GHz

LPF

TX RF Filter

Bank

44 MHz

HPF

Noise Reject

LPF

52 MHz

LPF

204 MHz

LPF

204 MHz

LPF

52 MHz

LPF

TX LO Filter

Bank

ADC

14 bit

TI ADS4246

DAC

16 bit

TI DAC3482

DAC

16 bit

TI DAC3482

31.75 dB Maximum

0.25 dB Step

31.75 dB Maximum

0.25 dB Step

ADI ADF4351

Synthesizer LO

RX RF Filter

Bank

RX LO Filter

Bank

RX IN

TX OUT

LO OUT

LO IN

31.75 dB Maximum

0.25 dB Step

12 dB

The following figure shows the connections between the NI 5791 and the LabVIEW FPGA
CLIP.

NI 5791R User Manual and Specifications | © National Instruments | 9

Summary of Contents for NI 5791R

Page 1: ...with 16 bit accuracy LO input and LO output connectors to support LO sharing for multiple channel applications Timing chip with clocking options from the backplane and the front panel Programmable att...

Page 2: ...on Guide and Specifications for installation instructions Note For EMC compliance operate this device according to the documentation The following figure shows an example of a properly connected NI Fl...

Page 3: ...nment 37 Installing PXI EMC Filler Panels 38 Where to Go for Support 39 Electromagnetic Compatibility Guidelines This product was tested and complies with the regulatory requirements and limits for el...

Page 4: ...778700 1 in adjacent chassis slots Related Information Installing PXI EMC Filler Panels on page 38 Connecting Cables 1 Use any shielded 50 SMA cable to connect signals to the connectors on the front...

Page 5: ...the Start menu and at ni com manuals Contains installation instructions for your NI FlexRIO system and specifications for your FPGA module NI 5791R User Manual and Specifications this document Availa...

Page 6: ...olated to 520 MS s Phase noise 94 dBc Hz 10 kHz offset 2 4 GHz carrier Dynamic range 105 dB Noise figure 8 dB at 2 GHz EVM 1 5 RMS Receive RX IP3 1 dBm at 2 GHz Transmit TX IP3 17 dBm at 2 GHz Configu...

Page 7: ...200MHz 4 4 GHz RF Transceiver RX IN LO OUT CLK OUT LO IN TX OUT CLK IN INSTRUMENTS NATIONAL RX IN Receive channel input 20 dBm maximum LO OUT Local oscillator output 12 dBm maximum 0 dBm nominal CLK...

Page 8: ...1 1 Bidirectional SE DIO data channel 10 DIO Port 1 2 Bidirectional SE DIO data channel 11 GND Ground reference for signals 12 DIO Port 1 3 Bidirectional SE DIO data channel 13 PFI 0 Bidirectional SE...

Page 9: ...MHz LPF TX LO Filter Bank ADC 14 bit TI ADS4246 DAC 16 bit TI DAC3482 DAC 16 bit TI DAC3482 31 75 dB Maximum 0 25 dB Step 31 75 dB Maximum 0 25 dB Step ADI ADF4351 Synthesizer LO RX RF Filter Bank RX...

Page 10: ...ata 0 DIO Port 1 Rd Data 1 DIO Port 1 Wr Data 1 DIO Port 1 Rd Data 2 DIO Port 1 Wr Data 2 DIO Port 1 Rd Data 3 DIO Port 1 Wr Data 3 LO Locked DIO Port 1 WE PFI 3 Wr Data PFI 0 3 WE PFI 3 Rd Data PFI 1...

Page 11: ...defined CLIP allows you to insert HDL IP into an FPGA target enabling VHDL code to communicate directly with an FPGA VI Socketed CLIP provides the same IP integration of the user defined CLIP but als...

Page 12: ...wing settings Internal Sample Clock Internal Sample Clock locked to an external Reference Clock though the CLK IN connector External Sample Clock through the CLK IN connector Internal Sample Clock loc...

Page 13: ...to use an existing LabVIEW FPGA example project to generate and acquire samples with the NI 5791R This example requires at least one SMA cable for connecting signals to your NI 5791R Note The example...

Page 14: ...bitfile name is based on the adapter module example type and FPGA module e Click the Select button f Click OK in the Configure Open FPGA VI Reference dialog box g Save the VI 7 On the front panel in...

Page 15: ...d select labview instr lib ni579x config v1 FPGA Public ni579x Config FPGA Template vi 11 Select File Save As 12 Select Copy Open Additional Copy and check Add Copy to your project name lvproj 13 Sele...

Page 16: ...FPGA VI Reference function to the Close FPGA VI Reference function 12 Save and close the VI 13 Save the project Run the Host VI 1 Open the front panel of your host VI 2 Click the Run button to run the...

Page 17: ...Configure your host VI to use the NI 579x Configuration Design Library using the following configuration 1 Create a Register Bus object for your device and initialize the session using ni579x Open vi...

Page 18: ...od must be greater than the maximum propagation delay of a signal from the master device to any slave device across the selected FPGA I O line The CPTR period must be the same across all devices Devic...

Page 19: ...treaming How Synchronization Works When you share triggers between multiple devices propagation delays on the signal path cause the trigger to arrive at different times on each device The synchronizat...

Page 20: ...ect settings in the system the project the host VI and the FPGA VI are configured as follows System settings Route the FPGA I O lines to all the devices Depending on your chassis size you may have to...

Page 21: ...d External through the CLK IN front panel connector Sourced through PXI CLK 579x Sample Projects The NI 5791 software contains sample projects that are a starting point for application development The...

Page 22: ...nt temperature ranges of 23 C 5 C with a 90 confidence level based on measurements taken during development or production Nominal values or supplemental information describe additional information abo...

Page 23: ...ttenuation Note Correction coefficients in EEPROM are valid only when the baseband amplifier is in the signal path Noise Density Table 7 Noise Density Center Frequency Average Noise Level dBm Hz Tempe...

Page 24: ...ncy Gain Compression Temperature 23 C 5 C dBm 200 MHz to 1 GHz 20 1 GHz to 2 GHz 18 2 GHz to 3 9 GHz 15 3 9 GHz to 4 4 GHz 12 Note Values are based on stimulus of two input tones spaced 100 MHz apart...

Page 25: ...1 5 kHz resolution bandwidth RBW RX LO Residual Power Note All values are nominal Table 9 Receiver LO Residual Power Center Frequency Residual Power Temperature 23 C 5 C dBFS 200 MHz to 1 GHz 42 1 GH...

Page 26: ...forms a single recent point I Q impairment self correction RX Third Order Intermodulation Distortion IP3 Note All values are nominal Table 11 RX IP3 Frequency Temperature 23 C 5 C dBm 200 MHz to 1 GHz...

Page 27: ...dBm Hz Dynamic Range dB 5 22 135 105 5 12 145 105 15 3 155 105 25 1 163 109 Note The signal level of each tone is set to 6 dB less than the reference level to prevent overload Dynamic range 2 3 IP3 N...

Page 28: ...al amplification For frequencies above 2 8 GHz NI recommends using external LO distribution amplifiers if more than two adapter modules share LOs CLK IN Front Panel Connector Frequency Reference Clock...

Page 29: ...olute maximum power 15 dBm Maximum DC power 0 5 VDC TX OUT Front Panel Connector Amplitude Characteristics Power range Output Noise floor to 8 dBm nominal Output resolution 0 25 dB nominal Amplitude s...

Page 30: ...t power level from 12 dBm to 4 dBm Figure 11 TX Output Power 1 0 500 0 m 500 0 m 0 0 1 0 1 5 2 5 2 0 3 0 3 5 4 5 4 0 5 0 5 5 6 0 6 5 7 5 7 0 8 0 9 0 8 5 9 5 10 0 1 0 G 1 5 G 2 0 G 2 5 G 3 0 G 3 5 G 4...

Page 31: ...GHz 1 7 1 Note The VSWR is measured with 10 dB of TX attenuation TX OUT Spurious Responses Third Order Intermodulation IP3 Note All values are typical Table 16 IP3 Frequency Temperature 23 C 5 C dBm...

Page 32: ...nuation TX Sideband Image Suppression Note All values are nominal Table 18 Image Suppression Frequency Temperature 23 C 5 C dBc 200 MHz to 1 GHz 50 1 GHz to 2 GHz 50 2 GHz to 3 GHz 50 3 GHz to 4 4 GHz...

Page 33: ...n1 250 kHz LO step size2 Integer mode 4 MHz 6 MHz 12 MHz 24 MHz step sizes Fractional mode 100 kHz step size Frequency Settling Time Settling time3 100 s per 50 MHz step 1 Tuning resolution combines L...

Page 34: ...Hz 1 kHz 90 10 kHz 94 100 kHz 104 1 MHz 130 10 MHz 140 Figure 12 Phase Noise 900 MHz 2 4 GHz 4 4 GHz Offset Frequency Hz Phase Noise dBc Hz 90 80 100 70 50 60 110 130 120 140 40 100 1 k 10 k 100 k 1...

Page 35: ...d on AUX I O Port 0 DIO 0 3 Port 1 DIO 0 3 and PFI 0 3 General Characteristics Number of channels 12 bidirectional 8 DIO and 4 PFI Connector type HDMI Interface standard 3 3 LVCMOS Interface logic Max...

Page 36: ...asurement control and laboratory use EN 61326 1 IEC 61326 1 Class A emissions Basic immunity EN 55011 CISPR 11 Group 1 Class A emissions AS NZS CISPR 11 Group 1 Class A emissions FCC 47 CFR Part 15B C...

Page 37: ...er to the Minimize Our Environmental Impact web page at ni com environment This page contains the environmental regulations and directives with which NI complies as well as other environmental informa...

Page 38: ...z 0 3 grms Nonoperating 5 Hz to 500 Hz 2 4 grms Tested in accordance with IEC 60068 2 64 Nonoperating test profile exceeds the requirements of MIL PRF 28800F Class 3 Installing PXI EMC Filler Panels T...

Page 39: ...rom troubleshooting and application development self help resources to email and phone assistance from NI Application Engineers A Declaration of Conformity DoC is our claim of compliance with the Coun...

Page 40: ...Other product and company names mentioned herein are trademarks or trade names of their respective companies For patents covering National Instruments products technology refer to the appropriate loca...

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