The edge is synchronized at the next CPTR edge. After all the device CPTRs are aligned, an
edge sent out on the FPGA I/O lines is read at the same clock cycle across all the devices.
Note
The quality of synchronization is only as good as the quality of Sample
Clock locking. Some static skew may exist. You can calibrate to eliminate this skew
if necessary.
The following figure shows the relationship between the time that the master device reads a
Reference Trigger (
Ref Trig
) and the time that all the devices read the synchronized version of
the Reference Trigger (
Synchronized Ref Trig
). This synchronization requires CPTR alignment
on all the devices.
Figure 8. Reading the Reference Triggers
Synchronized Ref Trig
CPTR Device B
Ref Trig
CPTR Device A
Sample Clock
Synchronization Checklist
Verify that the project settings in the system, the project, the host VI, and the FPGA VI are
configured as follows.
•
System settings:
–
Route the FPGA I/O lines to all the devices.
–
Depending on your chassis size, you may have to route PXI trigger lines using
Measurement & Automation Explorer (MAX). Refer to the
Measurement &
Automation Explorer (MAX) Help
at
ni.com/manuals
for more information about
routing PXI trigger lines with MAX.
•
Project settings:
–
Configure the adapter module IoModSyncClock (either PXI_CLK10 or DStarA) if
you are not driving the adapter module CLK IN connector.
–
Add the FPGA Reference Clock.
–
Configure the Reference Clock to have zero synchronization registers. In the
FPGA
IO Property
dialog box, set
Number of Synchronization Registers for Read
to 0.
–
Add the FPGA I/O lines that you are synchronizing. Do not remove synchronization
registers.
•
Host VI:
–
Configure the adapter module clock source based on the project settings.
–
Lock the adapter module clock to the clock source.
20 | NI 5791R User Manual and Specifications | ni.com
