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Figure 4. NI 5791 Connector Signals and CLIP Signal Block Diagram
NI 5791 Adapter Module
From RF
Mixer
To RF Mixer
DIO Port 0 (0)
From RF LO
RF Filters
RF LO
and Attenuators
SPI
DIO Port 0 (1)
DIO Port 0 (2)
DIO Port 0 (3)
DIO Port 1 (0)
DIO Port 1 (1)
DIO Port 1 (2)
DIO Port 1 (3)
PFI 0
PFI 1
PFI 2
PFI 3
A
UX I/O
ADC Clock
ADC Data
DAC
DAC3482
LabVIEW FPGA CLIP
DAC Clock
DAC Data
DAC
Interface
ADC
Interface
Rx I
Tx I
14
Register Bus Write
Register Write Data
Register Bus Read
Register Bus Read Data
Register Bus Address
Register Bus Idle
16
14
DIO Port 0 WE
DIO Port 0 Rd Data (0)
DIO Port 0 Wr Data (0)
DIO Port 0 Rd Data (1)
DIO Port 0 Wr Data (1)
DIO Port 0 Rd Data (2)
DIO Port 0 Wr Data (2)
DIO Port 0 Rd Data (3)
DIO Port 0 Wr Data (3)
DIO Port 1 Rd Data (0)
DIO Port 1 Wr Data (0)
DIO Port 1 Rd Data (1)
DIO Port 1 Wr Data (1)
DIO Port 1 Rd Data (2)
DIO Port 1 Wr Data (2)
DIO Port 1 Rd Data (3)
DIO Port 1 Wr Data (3)
LO Locked
DIO Port 1 WE
PFI 3 Wr Data
PFI <0..3> WE
PFI 3 Rd Data
PFI 1 Rd Data
PFI 1 Wr Data
PFI 2 Rd Data
PFI 2 Wr Data
PFI 0 Rd Data
PFI 0 Wr Data
4
User Data 1
User Command
User Command Commit
User Command Status
User Return
Initialization Done
User Error
User Command Idle
User Data 0
From RF
Mixer
To RF Mixer
PLL Locked
Sync Clock
Sample Clock 2x
Sample Clock
Sample Clock
Synchronize DAC
CLK IN
CLK OUT
SPI
Engine
PLL
Register
Bus
Calibration
EEPROM
Clock
DAC SPI
ADC SPI
DAC SPI
DAC
OUT3 OUT2
CP
OUT1
CLK1
REF IN
AD9511
CLK2
OUT 4
SPI
VCXO
Gain
PLL Loop
Filter
Enable VCXO
Enable PLL
External Sample CLK
External Ref CLK
AI Gain Control
RF Filter Control
Microcontroller
Rx Q
Tx Q
16
16
14
ADC
ADS4246
The following figure shows the NI 5791 low-pass filter bank.
10 | NI 5791R User Manual and Specifications | ni.com