Figure 6. CLIP and FPGA VI Relationship
Adapter Module
CLIP Socket
LabVIEW
FPGA VI
User-Defined
CLIP
NI FlexRIO FPGA Module
FPGA
Exter
nal
I/O Connector
Adapter
Module
Socketed
CLIP
User-Defined
CLIP
Fixed I/O
DRAM 0
CLIP Socket
Socketed
CLIP
DRAM 1
CLIP Socket
Socketed
CLIP
Fix
ed I/O
Fix
ed I/O
DRAM 0
DRAM 1
The NI 5791 ships with socketed CLIP items that add module I/O to the LabVIEW project.
5791 CLIP
The 5791 CLIP provides access to I and Q data for one receive channel and one transmit
channel. The CLIP also provides a User Command interface for common configurations of the
baseband clocking, programmable attenuators, receive amplifier, receive and transmit filters,
LO filters, and RF path. You can also import and export the LO.
Configure the baseband clocking using one of the following settings:
•
Internal Sample Clock
•
Internal Sample Clock locked to an external Reference Clock though the CLK IN
connector
•
External Sample Clock through the CLK IN connector
•
Internal Sample Clock locked to an external Reference Clock through the Sync Clock
This CLIP also contains a FAM Registers Bus interface, which is a low-level bus interface that
directly programs registers on all programmable devices, such as the analog-to-digital
converter (ADC) and the digital-to-analog converter (DAC). Programming registers on these
devices allows for more advanced configuration.
Note
You cannot configure the LO using the User Command interface. Use the
FAM Registers Bus interface to program the LO synthesizer, then use the User
Command interface to configure the LO filters.
Refer to the
NI FlexRIO Help
for more information about NI FlexRIO CLIP items,
configuring the NI 5791 with a socketed CLIP, and a list of available socketed CLIP signals.
12 | NI 5791R User Manual and Specifications | ni.com
