3-15
BIOS Setup
3-14
MS-9149 ATX Server Board
Advanced Chipset Features
DRAM Timing Selectable
Selects whether DRAM timing is controlled by the SPD (Serial Presence Detect)
EEPROM on the DRAM module. Setting to
By SPD
enables DRAM timing to
be determined automatically by BIOS based on the configurations on the SPD.
Selecting
Manual
allows users to configure these fields manually.
CAS Latency Time
This controls the timing delay (in clock cycles) before SDRAM starts a read
command after receiving it. Settings:
2
,
2.5, 3
(clocks).
2
(clocks) increases
the system performance the most while
3
(clocks) provides the most stable
performance.
Active to Precharge Delay
The field specifies the idle cycles before precharging an idle bank. Settings:
8, 7
,
6
,
5
(clocks).
DRAM RAS# to CAS# Delay
This field allows you to set the number of cycles for a timing delay between
the CAS and RAS strobe signals, used when DRAM is written to, read from
or refreshed. Fast speed offers faster performance while slow speed offers
more stable performance. Settings:
4, 3
,
2
(clocks).
NOTE
Change these settings only if you are familiar with the chipset.
this fie ld. With the t hermal monitorin g enabled, cloc k modulation co ntrolled
by the processor’s internal thermal sensor is also activated to keep the proces-
sor within allowable temperature limit. Setting options:
4 Min
,
8 Min
,
16 Min
,
32 Min
.
Thermal Management
This feature allows you to specify the thermal monitoring system. Settings are:
Thermal Monitoring 1 on die throttling
Thermal Monitoring 2 Ratio & VID transition
TM2 Bus Ratio (hidden for Prescott processor)
It represents the frequency (bus ratio) of the throttled performance state that
will be initiated when the on die sensor goes from not hot to hot. Key in a DEC
number between 0 and 255.
TM2 Bus VID (hidden for Prescott processor)
It represents the voltage of the throttled performance state that will be initiated
when the on die sensor goes from not hot to hot. Settings range from
0.8375V
to
1.6000V
.
