Motorola MC68HC05T16, Technical Data Manual

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MC68HC05T16 MOTOROLA
5-7
TIMERS
5
TOF - Timer Overflow Flag
1 (set) – Timer Overflow has occurred.
0 (clear) – No timer overflow has occurred.
This bit is set when the free-running counter overflows from $FFFF to $0000; a timer overflow
interrupt will occur, if TOIE (bit 5 in Timer Control register $10) is set. TOF is cleared by reading
the TSR and the counter low register ($19).
When using the timer overflow function and reading the free-running counter at random times to
measure an elapsed time, a problem may occur whereby the timer overflow flag is unintentionally
cleared if:
1) the timer status register is read or written when the TOF is set, and
2) the LSB of the free-running counter is read, but not for the purpose of
servicing the flag.
Reading the alternate counter register instead of the counter register will avoid this potential
problem.
TCAPS - Timer Capture State
1 (set) – TCAP pin is a logic high.
0 (clear) – TCAP pin is a logic low.
This bit reflects the logic level at the TCAP pin.
5.1.6 Programmable Timer Timing Diagrams
The relationships between the internal clock signals, the counter contents and the status of the
flag bits are shown in the following diagrams. It should be noted that the signals labelled ‘internal’
(processor clock, timer clocks and Reset) are not available to the user.
TPG
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